Nanoelectronic single-electron transistor circuits and architectures

Single-electron tunneling (SET) devices have been proposed as one promising candidate for future nanoelectronic integrated circuits. SETs have appealing properties for implementing ultra-dense and complex signal and image processing systems. The potential for very dense arrays of SET transistors makes them attractive for the realization of cellular non-linear network (CNN) circuits, where locally-connected cells may alleviate the interconnect problem facing conventional architectures as they scale. Herein, we investigate the use of nanoelectronic structures in CMOS-type digital circuits and in analog CNN architectures for potential application in future high-density and low-power CMOS-nanodevice hybrid circuits. We first present an overview of the operation of the SET transistor and simulation of SET circuits. We then discuss a programmable CMOS-type SET logic circuit based on a summing-node-inverter structure, followed by simple linear and 2-d SET-CNN architectures using the SET inverter topology as the basis for the non-linear transfer characteristics required of individual CNN elements. The simple SET-CNN cell acts as a summing node that is capacitively coupled to the inputs and outputs of nearest neighbour cells. Monte Carlo simulation results are then used to show CNN-like behaviour in attempting to realize different functionality such as shadowing, pattern forming, and horizontal-line detection. Within the context of these simple architectures, we discuss the speed and signal delay in SET non-linear circuits, and calculate the approximate power dissipation in a SET network.