MULTIPLE FAULT DETECTION FOR COMBINATIONAL LOGIC CIRCUITS.

Sik-Sang Yau, Shih Chien Yang

Research output: Contribution to journalArticle

10 Citations (Scopus)

Abstract

An algorithm for generating test sets to detect all the multiple stuck-at-faults in combinational logic circuits is presented. This algorithm generates a test set using a set of functions, called representative functions, which consists of much fewer functions than all possible multiple stuck-at fault functions, but is sufficient for test generation. Two different methods of finding such a set of representative functions are presented.

Original languageEnglish (US)
Pages (from-to)233-242
Number of pages10
JournalIEEE Transactions on Computers
VolumeC-24
Issue number3
StatePublished - Mar 1975
Externally publishedYes

Fingerprint

Combinatorial circuits
Logic circuits
Fault Detection
Fault detection
Logic
Test Set
Fault
Test Generation
Generating Set
Set theory
Sufficient

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

MULTIPLE FAULT DETECTION FOR COMBINATIONAL LOGIC CIRCUITS. / Yau, Sik-Sang; Yang, Shih Chien.

In: IEEE Transactions on Computers, Vol. C-24, No. 3, 03.1975, p. 233-242.

Research output: Contribution to journalArticle

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