Multi-tiered approach to improving the reliability of multi-level cell pram

Chengen Yang, Yunus Emre, Yu Cao, Chaitali Chakrabarti

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

Phase change RAM (PRAM) is a promising memory technology because of its fast read access time, high storage density and very low standby power. Multi-level Cell (MLC) PRAM which has been introduced to further improve the storage density, comes at a price of lower reliability. This paper focuses on a cost-effective solution for improving the reliability of MLC-PRAM. As the first step, we study in detail the causes of hard and soft errors and develop error models to capture these effects. Next we propose a multi-tiered approach that spans architecture, circuit and system levels to increase the reliability. At the architecture level, we use a combination of Gray code encoding and 2-bit interleaving to partition the errors so that a lower strength error correction coding (ECC) can be used for half of the bits that are in the odd block. We use subblock flipping and threshold resistance tuning to reduce the number of errors in the even block. For even higher reliability, we use a simple BCH based ECC on top of these techniques. We show that the propose multi-tiered approach enables us to use a low cost ECC with 2-error correction capability (t=2) instead of one with t=8 to achieve a block failure rate of 10-8.

Original languageEnglish (US)
Title of host publicationIEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
Pages114-119
Number of pages6
DOIs
StatePublished - 2012
Event2012 IEEE Workshop on Signal Processing Systems, SiPS 2012 - Quebec City, QC, Canada
Duration: Oct 17 2012Oct 19 2012

Other

Other2012 IEEE Workshop on Signal Processing Systems, SiPS 2012
CountryCanada
CityQuebec City, QC
Period10/17/1210/19/12

Fingerprint

Error correction
Error Correction
Phase Change
Random access storage
Coding
Cell
Soft Error
Gray Code
Error Model
Interleaving
Failure Rate
Costs
Tuning
Encoding
Odd
Partition
Data storage equipment
Networks (circuits)
Architecture

Keywords

  • Error correction codes
  • Multi-level cell
  • Multi-tiered approach
  • Phase change memory

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Signal Processing
  • Applied Mathematics
  • Hardware and Architecture

Cite this

Yang, C., Emre, Y., Cao, Y., & Chakrabarti, C. (2012). Multi-tiered approach to improving the reliability of multi-level cell pram. In IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation (pp. 114-119). [6363192] https://doi.org/10.1109/SiPS.2012.46

Multi-tiered approach to improving the reliability of multi-level cell pram. / Yang, Chengen; Emre, Yunus; Cao, Yu; Chakrabarti, Chaitali.

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation. 2012. p. 114-119 6363192.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Yang, C, Emre, Y, Cao, Y & Chakrabarti, C 2012, Multi-tiered approach to improving the reliability of multi-level cell pram. in IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation., 6363192, pp. 114-119, 2012 IEEE Workshop on Signal Processing Systems, SiPS 2012, Quebec City, QC, Canada, 10/17/12. https://doi.org/10.1109/SiPS.2012.46
Yang C, Emre Y, Cao Y, Chakrabarti C. Multi-tiered approach to improving the reliability of multi-level cell pram. In IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation. 2012. p. 114-119. 6363192 https://doi.org/10.1109/SiPS.2012.46
Yang, Chengen ; Emre, Yunus ; Cao, Yu ; Chakrabarti, Chaitali. / Multi-tiered approach to improving the reliability of multi-level cell pram. IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation. 2012. pp. 114-119
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