Multi-tiered approach to improving the reliability of multi-level cell pram

Phase change RAM (PRAM) is a promising memory technology because of its fast read access time, high storage density and very low standby power. Multi-level Cell (MLC) PRAM which has been introduced to further improve the storage density, comes at a price of lower reliability. This paper focuses on a cost-effective solution for improving the reliability of MLC-PRAM. As the first step, we study in detail the causes of hard and soft errors and develop error models to capture these effects. Next we propose a multi-tiered approach that spans architecture, circuit and system levels to increase the reliability. At the architecture level, we use a combination of Gray code encoding and 2-bit interleaving to partition the errors so that a lower strength error correction coding (ECC) can be used for half of the bits that are in the odd block. We use subblock flipping and threshold resistance tuning to reduce the number of errors in the even block. For even higher reliability, we use a simple BCH based ECC on top of these techniques. We show that the propose multi-tiered approach enables us to use a low cost ECC with 2-error correction capability (t=2) instead of one with t=8 to achieve a block failure rate of 10^-8.