TY - GEN
T1 - Multi-product floorplan and uncore design framework for chip multiprocessors
AU - Escalante, Marco
AU - Kahng, Andrew B.
AU - Kishinevsky, Michael
AU - Ogras, Umit
AU - Samadi, Kambiz
N1 - Publisher Copyright:
Copyright © 2015 by the Institute of Electrical and Electronics Engineers, Inc.
PY - 2015/7/28
Y1 - 2015/7/28
N2 - Chip multiprocessors (CMPs) for server and high-performance computing markets are offered in multiple classes to satisfy various power, performance and cost requirements. As the number of processor cores on a single die grows, resources outside the "core", such as the distributed last-level cache, on-chip memory controllers and network-on-chip (NoC) interconnecting these resources, which constitute the "uncore", play an increasingly important role. While it is crucial to optimize the floorplan and uncore of each product class to achieve the best power-performance tradeoff, independent optimization may greatly increase the design effort, and undermine the savings ultimately achieved with a given total amount of optimization effort. This paper presents a novel multi-product optimization framework for next generation CMPs. Unlike traditional chip optimization techniques, we optimize the floorplan of multiple product classes at once, and ensure that the smaller floorplans can be obtained from larger ones by optimally removing, i.e., chopping, the unused parts.
AB - Chip multiprocessors (CMPs) for server and high-performance computing markets are offered in multiple classes to satisfy various power, performance and cost requirements. As the number of processor cores on a single die grows, resources outside the "core", such as the distributed last-level cache, on-chip memory controllers and network-on-chip (NoC) interconnecting these resources, which constitute the "uncore", play an increasingly important role. While it is crucial to optimize the floorplan and uncore of each product class to achieve the best power-performance tradeoff, independent optimization may greatly increase the design effort, and undermine the savings ultimately achieved with a given total amount of optimization effort. This paper presents a novel multi-product optimization framework for next generation CMPs. Unlike traditional chip optimization techniques, we optimize the floorplan of multiple product classes at once, and ensure that the smaller floorplans can be obtained from larger ones by optimally removing, i.e., chopping, the unused parts.
UR - http://www.scopus.com/inward/record.url?scp=84944705166&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84944705166&partnerID=8YFLogxK
U2 - 10.1109/SLIP.2015.7171713
DO - 10.1109/SLIP.2015.7171713
M3 - Conference contribution
AN - SCOPUS:84944705166
T3 - International Workshop on System Level Interconnect Prediction, SLIP
BT - 2015 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2015
PB - Association for Computing Machinery
T2 - ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2015
Y2 - 6 June 2015
ER -