Multi-product floorplan and uncore design framework for chip multiprocessors

Marco Escalante, Andrew B. Kahng, Michael Kishinevsky, Umit Ogras, Kambiz Samadi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Chip multiprocessors (CMPs) for server and high-performance computing markets are offered in multiple classes to satisfy various power, performance and cost requirements. As the number of processor cores on a single die grows, resources outside the "core", such as the distributed last-level cache, on-chip memory controllers and network-on-chip (NoC) interconnecting these resources, which constitute the "uncore", play an increasingly important role. While it is crucial to optimize the floorplan and uncore of each product class to achieve the best power-performance tradeoff, independent optimization may greatly increase the design effort, and undermine the savings ultimately achieved with a given total amount of optimization effort. This paper presents a novel multi-product optimization framework for next generation CMPs. Unlike traditional chip optimization techniques, we optimize the floorplan of multiple product classes at once, and ensure that the smaller floorplans can be obtained from larger ones by optimally removing, i.e., chopping, the unused parts.

Original languageEnglish (US)
Title of host publicationInternational Workshop on System Level Interconnect Prediction, SLIP
PublisherAssociation for Computing Machinery
Volume2015-July
ISBN (Print)9781467381895
DOIs
StatePublished - Jul 28 2015
EventACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2015 - San Francisco, United States
Duration: Jun 6 2015 → …

Other

OtherACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2015
CountryUnited States
CitySan Francisco
Period6/6/15 → …

Fingerprint

Chip multiprocessors
Optimization
Chip
Optimise
Resources
Cache
Optimization Techniques
Die
Server
High Performance
Trade-offs
Controller
Servers
Computing
Requirements
Costs
Data storage equipment
Controllers
Class
Design

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Applied Mathematics

Cite this

Escalante, M., Kahng, A. B., Kishinevsky, M., Ogras, U., & Samadi, K. (2015). Multi-product floorplan and uncore design framework for chip multiprocessors. In International Workshop on System Level Interconnect Prediction, SLIP (Vol. 2015-July). [7171713] Association for Computing Machinery. https://doi.org/10.1109/SLIP.2015.7171713

Multi-product floorplan and uncore design framework for chip multiprocessors. / Escalante, Marco; Kahng, Andrew B.; Kishinevsky, Michael; Ogras, Umit; Samadi, Kambiz.

International Workshop on System Level Interconnect Prediction, SLIP. Vol. 2015-July Association for Computing Machinery, 2015. 7171713.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Escalante, M, Kahng, AB, Kishinevsky, M, Ogras, U & Samadi, K 2015, Multi-product floorplan and uncore design framework for chip multiprocessors. in International Workshop on System Level Interconnect Prediction, SLIP. vol. 2015-July, 7171713, Association for Computing Machinery, ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2015, San Francisco, United States, 6/6/15. https://doi.org/10.1109/SLIP.2015.7171713
Escalante M, Kahng AB, Kishinevsky M, Ogras U, Samadi K. Multi-product floorplan and uncore design framework for chip multiprocessors. In International Workshop on System Level Interconnect Prediction, SLIP. Vol. 2015-July. Association for Computing Machinery. 2015. 7171713 https://doi.org/10.1109/SLIP.2015.7171713
Escalante, Marco ; Kahng, Andrew B. ; Kishinevsky, Michael ; Ogras, Umit ; Samadi, Kambiz. / Multi-product floorplan and uncore design framework for chip multiprocessors. International Workshop on System Level Interconnect Prediction, SLIP. Vol. 2015-July Association for Computing Machinery, 2015.
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