Multi-level logic optimization for low power using local logic transformations

In this paper we present an efficient technique to reduce the switching activity in a CMOS combinational logic network based on local logic transformations. These transformations consist of adding redundant connections or gates so as to reduce the switching activity. Simple and efficient procedures, based on logic implication, for identifying the sources and targets of the redundant connections are presented. Additionally, procedures that permit the designer to trade-off power and delay after the transformations are described. Results of experiments on the MCNC benchmark circuits are given. The results indicate that significant reduction of the switching activities of a CMOS combinational circuit can be achieved with a very low area overhead and low computational cost.