TY - JOUR
T1 - MRIMA
T2 - An MRAM-Based In-Memory Accelerator
AU - Angizi, Shaahin
AU - He, Zhezhi
AU - Awad, Amro
AU - Fan, Deliang
N1 - Funding Information:
Manuscript received October 15, 2018; revised February 9, 2019; accepted March 10, 2019. Date of publication March 27, 2019; date of current version April 21, 2020. This work was supported in part by the National Science Foundation under Grant 1740126, and in part by the Semiconductor Research Corporation nCORE. This paper was recommended by Associate Editor J. Henkel. (Corresponding author: Shaahin Angizi.) The authors are with the Department of Electrical and Computer Engineering, University of Central Florida, Orlando, FL 32816 USA (e-mail: angizi@knights.ucf.edu; elliot.he@knights.ucf.edu; amro.awad@ucf.edu; dfan@ucf.edu). Digital Object Identifier 10.1109/TCAD.2019.2907886
Publisher Copyright:
© 1982-2012 IEEE.
PY - 2020/5
Y1 - 2020/5
N2 - In this paper, we propose MRIMA, as a novel magnetic RAM (MRAM)-based in-memory accelerator for nonvolatile, flexible, and efficient in-memory computing. MRIMA transforms current spin transfer torque magnetic random access memory (STT-MRAM) arrays to massively parallel computational units capable of working as both nonvolatile memory and in-memory logic. Instead of integrating complex logic units in cost-sensitive memory, MRIMA exploits hardware-friendly bit-line computing methods to implement complete Boolean logic functions between operands within a memory array in a single clock cycle, overcoming the multicycle logic issue in contemporary processing-in-memory (PIM) platforms. We present practical case studies to demonstrate MRIMA's acceleration for binary-weight and low bit-width convolutional neural networks (CNNs) as well as data encryption. Our device-to-architecture co-simulation results on CNN acceleration demonstrate that MRIMA can obtain 1.7 {\times } better energy-efficiency and 11.2{\times } speed-up compared to ASICs, and 1.8 {\times } better energy-efficiency and 2.4 {\times } speed-up over the best DRAM-based PIM solutions. As an advanced encryption standard (AES) in-memory encryption engine, MRIMA shows 77% and 21% lower energy consumption compared to CMOS-ASIC and recent domain-wall-based design, respectively.
AB - In this paper, we propose MRIMA, as a novel magnetic RAM (MRAM)-based in-memory accelerator for nonvolatile, flexible, and efficient in-memory computing. MRIMA transforms current spin transfer torque magnetic random access memory (STT-MRAM) arrays to massively parallel computational units capable of working as both nonvolatile memory and in-memory logic. Instead of integrating complex logic units in cost-sensitive memory, MRIMA exploits hardware-friendly bit-line computing methods to implement complete Boolean logic functions between operands within a memory array in a single clock cycle, overcoming the multicycle logic issue in contemporary processing-in-memory (PIM) platforms. We present practical case studies to demonstrate MRIMA's acceleration for binary-weight and low bit-width convolutional neural networks (CNNs) as well as data encryption. Our device-to-architecture co-simulation results on CNN acceleration demonstrate that MRIMA can obtain 1.7 {\times } better energy-efficiency and 11.2{\times } speed-up compared to ASICs, and 1.8 {\times } better energy-efficiency and 2.4 {\times } speed-up over the best DRAM-based PIM solutions. As an advanced encryption standard (AES) in-memory encryption engine, MRIMA shows 77% and 21% lower energy consumption compared to CMOS-ASIC and recent domain-wall-based design, respectively.
KW - Advanced encryption standard (AES)
KW - convolutional neural network (CNN)
KW - in-memory processing platform
KW - spintronics
UR - http://www.scopus.com/inward/record.url?scp=85063673976&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85063673976&partnerID=8YFLogxK
U2 - 10.1109/TCAD.2019.2907886
DO - 10.1109/TCAD.2019.2907886
M3 - Article
AN - SCOPUS:85063673976
SN - 0278-0070
VL - 39
SP - 1123
EP - 1136
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IS - 5
M1 - 8675492
ER -