TY - GEN
T1 - Motion estimation architecture for video compression
AU - Chan, Eric
AU - Panchanathan, Sethuraman
PY - 1993/1/1
Y1 - 1993/1/1
N2 - In this paper, we propose a VLSI architecture which implements the full search block matching motion estimation algorithm in real-time. The architecture consists of a 2-D structure of basic cells (BC's) where each BC is capable of computing the mean absolute error. The proposed architecture is modular, simple and regular in structure and is hence very attractive for VLSI implementation as a codes.
AB - In this paper, we propose a VLSI architecture which implements the full search block matching motion estimation algorithm in real-time. The architecture consists of a 2-D structure of basic cells (BC's) where each BC is capable of computing the mean absolute error. The proposed architecture is modular, simple and regular in structure and is hence very attractive for VLSI implementation as a codes.
UR - http://www.scopus.com/inward/record.url?scp=0027150829&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0027150829&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0027150829
SN - 0780308433
T3 - Digest of Technical Papers - IEEE International Conference on Consumer Electronics
SP - 72
EP - 73
BT - Digest of Technical Papers - IEEE International Conference on Consumer Electronics
PB - Publ by IEEE
T2 - Proceedings of the IEEE 1993 International Conference on Consumer Electronics
Y2 - 8 June 1993 through 10 June 1993
ER -