Motion estimation architecture for video compression

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we propose a VLSI architecture which implements the full search block matching motion estimation algorithm in real-time. The architecture consists of a 2-D structure of basic cells (BC's) where each BC is capable of computing the mean absolute error. The proposed architecture is modular, simple and regular in structure and is hence very attractive for VLSI implementation as a codes.

Original languageEnglish (US)
Title of host publicationDigest of Technical Papers - IEEE International Conference on Consumer Electronics
PublisherPubl by IEEE
Pages72-73
Number of pages2
ISBN (Print)0780308433
StatePublished - 1993
Externally publishedYes
EventProceedings of the IEEE 1993 International Conference on Consumer Electronics - Rosemont, IL,USA
Duration: Jun 8 1993Jun 10 1993

Other

OtherProceedings of the IEEE 1993 International Conference on Consumer Electronics
CityRosemont, IL,USA
Period6/8/936/10/93

Fingerprint

Motion estimation
Image compression

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Industrial and Manufacturing Engineering

Cite this

Chan, E., & Panchanathan, S. (1993). Motion estimation architecture for video compression. In Digest of Technical Papers - IEEE International Conference on Consumer Electronics (pp. 72-73). Publ by IEEE.

Motion estimation architecture for video compression. / Chan, Eric; Panchanathan, Sethuraman.

Digest of Technical Papers - IEEE International Conference on Consumer Electronics. Publ by IEEE, 1993. p. 72-73.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Chan, E & Panchanathan, S 1993, Motion estimation architecture for video compression. in Digest of Technical Papers - IEEE International Conference on Consumer Electronics. Publ by IEEE, pp. 72-73, Proceedings of the IEEE 1993 International Conference on Consumer Electronics, Rosemont, IL,USA, 6/8/93.
Chan E, Panchanathan S. Motion estimation architecture for video compression. In Digest of Technical Papers - IEEE International Conference on Consumer Electronics. Publ by IEEE. 1993. p. 72-73
Chan, Eric ; Panchanathan, Sethuraman. / Motion estimation architecture for video compression. Digest of Technical Papers - IEEE International Conference on Consumer Electronics. Publ by IEEE, 1993. pp. 72-73
@inproceedings{2f4c2951550e4b8fb49ece18059e5c6c,
title = "Motion estimation architecture for video compression",
abstract = "In this paper, we propose a VLSI architecture which implements the full search block matching motion estimation algorithm in real-time. The architecture consists of a 2-D structure of basic cells (BC's) where each BC is capable of computing the mean absolute error. The proposed architecture is modular, simple and regular in structure and is hence very attractive for VLSI implementation as a codes.",
author = "Eric Chan and Sethuraman Panchanathan",
year = "1993",
language = "English (US)",
isbn = "0780308433",
pages = "72--73",
booktitle = "Digest of Technical Papers - IEEE International Conference on Consumer Electronics",
publisher = "Publ by IEEE",

}

TY - GEN

T1 - Motion estimation architecture for video compression

AU - Chan, Eric

AU - Panchanathan, Sethuraman

PY - 1993

Y1 - 1993

N2 - In this paper, we propose a VLSI architecture which implements the full search block matching motion estimation algorithm in real-time. The architecture consists of a 2-D structure of basic cells (BC's) where each BC is capable of computing the mean absolute error. The proposed architecture is modular, simple and regular in structure and is hence very attractive for VLSI implementation as a codes.

AB - In this paper, we propose a VLSI architecture which implements the full search block matching motion estimation algorithm in real-time. The architecture consists of a 2-D structure of basic cells (BC's) where each BC is capable of computing the mean absolute error. The proposed architecture is modular, simple and regular in structure and is hence very attractive for VLSI implementation as a codes.

UR - http://www.scopus.com/inward/record.url?scp=0027150829&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0027150829&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0027150829

SN - 0780308433

SP - 72

EP - 73

BT - Digest of Technical Papers - IEEE International Conference on Consumer Electronics

PB - Publ by IEEE

ER -