Motion estimation architecture for video compression

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we propose a VLSI architecture which implements the full search block matching motion estimation algorithm in real-time. The architecture consists of a 2-D structure of basic cells (BC's) where each BC is capable of computing the mean absolute error. The proposed architecture is modular, simple and regular in structure and is hence very attractive for VLSI implementation as a codes.

Original languageEnglish (US)
Title of host publicationDigest of Technical Papers - IEEE International Conference on Consumer Electronics
PublisherPubl by IEEE
Pages72-73
Number of pages2
ISBN (Print)0780308433
StatePublished - Jan 1 1993
Externally publishedYes
EventProceedings of the IEEE 1993 International Conference on Consumer Electronics - Rosemont, IL,USA
Duration: Jun 8 1993Jun 10 1993

Publication series

NameDigest of Technical Papers - IEEE International Conference on Consumer Electronics
ISSN (Print)0747-668X

Other

OtherProceedings of the IEEE 1993 International Conference on Consumer Electronics
CityRosemont, IL,USA
Period6/8/936/10/93

ASJC Scopus subject areas

  • Industrial and Manufacturing Engineering
  • Electrical and Electronic Engineering

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