Abstract
In this paper, we propose a VLSI architecture which implements the full search block matching motion estimation algorithm in real-time. The architecture consists of a 2-D structure of basic cells (BC's) where each BC is capable of computing the mean absolute error. The interblock dependency is exploited and hence the architecture can meet the real time requirement in various applications. Most importantly, the architecture is simple, modular and cascadable. This makes possible VLSI implementation as a codec.
Original language | English (US) |
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Pages (from-to) | 292-297 |
Number of pages | 6 |
Journal | IEEE Transactions on Consumer Electronics |
Volume | 39 |
Issue number | 3 |
DOIs | |
State | Published - Aug 1993 |
Externally published | Yes |
ASJC Scopus subject areas
- Media Technology
- Electrical and Electronic Engineering