Device simulations are essential to explore new device designs, optimize performance and understand underlying physics. As we scale the gate lengths of deep sub micrometer devices, there are always contradicting requirements of increased hot carrier reliability and reduced short channel effects. These contradicting requirements have led semiconductor device engineers towards asymmetric device structures. Typical methods employed to simulate such devices include commercial simulation software such as ATLAS and Monte Carlo particle-based simulations. In this work, we have simulated conventional and highly asymmetric 100nm n-channel Focused-Ion-Beam MOS device(FIBMOS). As a second effort we have pushed the gate length of this asymmetric device down to 50nm and compared the results with that of a conventional MOS device of the same gate length.