Monolithically Integrated RRAM- And CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning

Shihui Yin, Jae Sun Seo, Yulhwa Kim, Xu Han, Hugh Barnaby, Shimeng Yu, Yandong Luo, Wangxin He, Xiaoyu Sun, Jae Joon Kim

Research output: Contribution to journalArticle

Abstract

Resistive RAM (RRAM) has been presented as a promising memory technology toward deep neural network (DNN) hardware design, with nonvolatility, high density, high ON/OFF ratio, and compatibility with logic process. However, prior RRAM works for DNNs have shown limitations on parallelism for in-memory computing, array efficiency with large peripheral circuits, multilevel analog operation, and demonstration of monolithic integration. In this article, we propose circuit-/device-level optimizations to improve the energy and density of RRAM-based in-memory computing architectures. We report experimental results based on prototype chip design of 128 × 64 RRAM arrays and CMOS peripheral circuits, where RRAM devices are monolithically integrated in a commercial 90-nm CMOS technology. We demonstrate the CMOS peripheral circuit optimization using input-splitting scheme and investigate the implication of higher low resistance state on energy efficiency and robustness. Employing the proposed techniques, we demonstrate RRAM-based in-memory computing with up to 116.0 TOPS/W energy efficiency and 84.2% CIFAR-10 accuracy. Furthermore, we investigate four-level programming with single RRAM device, and report the system-level performance and DNN accuracy results using circuit-level benchmark simulator NeuroSim.

Original languageEnglish (US)
Article number8894568
Pages (from-to)54-63
Number of pages10
JournalIEEE Micro
Volume39
Issue number6
DOIs
StatePublished - Nov 1 2019

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Data storage equipment
Networks (circuits)
Energy efficiency
Computer peripheral equipment
Computer hardware
Deep learning
RRAM
Demonstrations
Simulators
Deep neural networks

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Monolithically Integrated RRAM- And CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning. / Yin, Shihui; Seo, Jae Sun; Kim, Yulhwa; Han, Xu; Barnaby, Hugh; Yu, Shimeng; Luo, Yandong; He, Wangxin; Sun, Xiaoyu; Kim, Jae Joon.

In: IEEE Micro, Vol. 39, No. 6, 8894568, 01.11.2019, p. 54-63.

Research output: Contribution to journalArticle

Yin, Shihui ; Seo, Jae Sun ; Kim, Yulhwa ; Han, Xu ; Barnaby, Hugh ; Yu, Shimeng ; Luo, Yandong ; He, Wangxin ; Sun, Xiaoyu ; Kim, Jae Joon. / Monolithically Integrated RRAM- And CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning. In: IEEE Micro. 2019 ; Vol. 39, No. 6. pp. 54-63.
@article{c85b3740649c4ba8bb22d723a26dc6c9,
title = "Monolithically Integrated RRAM- And CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning",
abstract = "Resistive RAM (RRAM) has been presented as a promising memory technology toward deep neural network (DNN) hardware design, with nonvolatility, high density, high ON/OFF ratio, and compatibility with logic process. However, prior RRAM works for DNNs have shown limitations on parallelism for in-memory computing, array efficiency with large peripheral circuits, multilevel analog operation, and demonstration of monolithic integration. In this article, we propose circuit-/device-level optimizations to improve the energy and density of RRAM-based in-memory computing architectures. We report experimental results based on prototype chip design of 128 × 64 RRAM arrays and CMOS peripheral circuits, where RRAM devices are monolithically integrated in a commercial 90-nm CMOS technology. We demonstrate the CMOS peripheral circuit optimization using input-splitting scheme and investigate the implication of higher low resistance state on energy efficiency and robustness. Employing the proposed techniques, we demonstrate RRAM-based in-memory computing with up to 116.0 TOPS/W energy efficiency and 84.2{\%} CIFAR-10 accuracy. Furthermore, we investigate four-level programming with single RRAM device, and report the system-level performance and DNN accuracy results using circuit-level benchmark simulator NeuroSim.",
author = "Shihui Yin and Seo, {Jae Sun} and Yulhwa Kim and Xu Han and Hugh Barnaby and Shimeng Yu and Yandong Luo and Wangxin He and Xiaoyu Sun and Kim, {Jae Joon}",
year = "2019",
month = "11",
day = "1",
doi = "10.1109/MM.2019.2943047",
language = "English (US)",
volume = "39",
pages = "54--63",
journal = "IEEE Micro",
issn = "0272-1732",
publisher = "IEEE Computer Society",
number = "6",

}

TY - JOUR

T1 - Monolithically Integrated RRAM- And CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning

AU - Yin, Shihui

AU - Seo, Jae Sun

AU - Kim, Yulhwa

AU - Han, Xu

AU - Barnaby, Hugh

AU - Yu, Shimeng

AU - Luo, Yandong

AU - He, Wangxin

AU - Sun, Xiaoyu

AU - Kim, Jae Joon

PY - 2019/11/1

Y1 - 2019/11/1

N2 - Resistive RAM (RRAM) has been presented as a promising memory technology toward deep neural network (DNN) hardware design, with nonvolatility, high density, high ON/OFF ratio, and compatibility with logic process. However, prior RRAM works for DNNs have shown limitations on parallelism for in-memory computing, array efficiency with large peripheral circuits, multilevel analog operation, and demonstration of monolithic integration. In this article, we propose circuit-/device-level optimizations to improve the energy and density of RRAM-based in-memory computing architectures. We report experimental results based on prototype chip design of 128 × 64 RRAM arrays and CMOS peripheral circuits, where RRAM devices are monolithically integrated in a commercial 90-nm CMOS technology. We demonstrate the CMOS peripheral circuit optimization using input-splitting scheme and investigate the implication of higher low resistance state on energy efficiency and robustness. Employing the proposed techniques, we demonstrate RRAM-based in-memory computing with up to 116.0 TOPS/W energy efficiency and 84.2% CIFAR-10 accuracy. Furthermore, we investigate four-level programming with single RRAM device, and report the system-level performance and DNN accuracy results using circuit-level benchmark simulator NeuroSim.

AB - Resistive RAM (RRAM) has been presented as a promising memory technology toward deep neural network (DNN) hardware design, with nonvolatility, high density, high ON/OFF ratio, and compatibility with logic process. However, prior RRAM works for DNNs have shown limitations on parallelism for in-memory computing, array efficiency with large peripheral circuits, multilevel analog operation, and demonstration of monolithic integration. In this article, we propose circuit-/device-level optimizations to improve the energy and density of RRAM-based in-memory computing architectures. We report experimental results based on prototype chip design of 128 × 64 RRAM arrays and CMOS peripheral circuits, where RRAM devices are monolithically integrated in a commercial 90-nm CMOS technology. We demonstrate the CMOS peripheral circuit optimization using input-splitting scheme and investigate the implication of higher low resistance state on energy efficiency and robustness. Employing the proposed techniques, we demonstrate RRAM-based in-memory computing with up to 116.0 TOPS/W energy efficiency and 84.2% CIFAR-10 accuracy. Furthermore, we investigate four-level programming with single RRAM device, and report the system-level performance and DNN accuracy results using circuit-level benchmark simulator NeuroSim.

UR - http://www.scopus.com/inward/record.url?scp=85075013149&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85075013149&partnerID=8YFLogxK

U2 - 10.1109/MM.2019.2943047

DO - 10.1109/MM.2019.2943047

M3 - Article

AN - SCOPUS:85075013149

VL - 39

SP - 54

EP - 63

JO - IEEE Micro

JF - IEEE Micro

SN - 0272-1732

IS - 6

M1 - 8894568

ER -