TY - JOUR
T1 - Monolithically Integrated RRAM- And CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning
AU - Yin, Shihui
AU - Seo, Jae Sun
AU - Kim, Yulhwa
AU - Han, Xu
AU - Barnaby, Hugh
AU - Yu, Shimeng
AU - Luo, Yandong
AU - He, Wangxin
AU - Sun, Xiaoyu
AU - Kim, Jae Joon
N1 - Funding Information:
Shimeng Yu is an associate professor in the School of Electrical and Computer Engineering, Georgia Institute of Technology. His research interests are nanoelectronic devices and circuits for energy-efficient computing systems. He was a recipient of the NSF CAREER Award in 2016, the IEEE Electron Devices Society (EDS) Early Career Award in 2017, and the Semiconductor Research Corporation (SRC) Young Faculty Award in 2019. He is a senior member of IEEE. Contact him at: shimeng.yu@ece.gatech.edu.
Funding Information:
The authors would like to thank Winbond Electronics for chip fabrication support. This work was supported in part by NSF-SRC-E2CDA under Contract 2018-NC-2762B; by the National Science Foundation (NSF) under Grant 1652866, Grant 1715443, and Grant 1740225; in part by JUMP C-BRIC and ASCENT programs (SRC programs sponsored by DARPA); and in part by the Nano-Material Technology Development Program through the National Research Foundation of Korea funded by the Ministry of Science, ICT (NRF-2016M3A7B4910249).
Publisher Copyright:
© 1981-2012 IEEE.
PY - 2019/11/1
Y1 - 2019/11/1
N2 - Resistive RAM (RRAM) has been presented as a promising memory technology toward deep neural network (DNN) hardware design, with nonvolatility, high density, high ON/OFF ratio, and compatibility with logic process. However, prior RRAM works for DNNs have shown limitations on parallelism for in-memory computing, array efficiency with large peripheral circuits, multilevel analog operation, and demonstration of monolithic integration. In this article, we propose circuit-/device-level optimizations to improve the energy and density of RRAM-based in-memory computing architectures. We report experimental results based on prototype chip design of 128 × 64 RRAM arrays and CMOS peripheral circuits, where RRAM devices are monolithically integrated in a commercial 90-nm CMOS technology. We demonstrate the CMOS peripheral circuit optimization using input-splitting scheme and investigate the implication of higher low resistance state on energy efficiency and robustness. Employing the proposed techniques, we demonstrate RRAM-based in-memory computing with up to 116.0 TOPS/W energy efficiency and 84.2% CIFAR-10 accuracy. Furthermore, we investigate four-level programming with single RRAM device, and report the system-level performance and DNN accuracy results using circuit-level benchmark simulator NeuroSim.
AB - Resistive RAM (RRAM) has been presented as a promising memory technology toward deep neural network (DNN) hardware design, with nonvolatility, high density, high ON/OFF ratio, and compatibility with logic process. However, prior RRAM works for DNNs have shown limitations on parallelism for in-memory computing, array efficiency with large peripheral circuits, multilevel analog operation, and demonstration of monolithic integration. In this article, we propose circuit-/device-level optimizations to improve the energy and density of RRAM-based in-memory computing architectures. We report experimental results based on prototype chip design of 128 × 64 RRAM arrays and CMOS peripheral circuits, where RRAM devices are monolithically integrated in a commercial 90-nm CMOS technology. We demonstrate the CMOS peripheral circuit optimization using input-splitting scheme and investigate the implication of higher low resistance state on energy efficiency and robustness. Employing the proposed techniques, we demonstrate RRAM-based in-memory computing with up to 116.0 TOPS/W energy efficiency and 84.2% CIFAR-10 accuracy. Furthermore, we investigate four-level programming with single RRAM device, and report the system-level performance and DNN accuracy results using circuit-level benchmark simulator NeuroSim.
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U2 - 10.1109/MM.2019.2943047
DO - 10.1109/MM.2019.2943047
M3 - Article
AN - SCOPUS:85075013149
SN - 0272-1732
VL - 39
SP - 54
EP - 63
JO - IEEE Micro
JF - IEEE Micro
IS - 6
M1 - 8894568
ER -