Modeling the electrical effects of metal dishing due to CMP for on-chip interconnect optimization

Runzi Chang; Yu Cao; Costas J. Spanos

doi:10.1109/TED.2004.834898

Modeling the electrical effects of metal dishing due to CMP for on-chip interconnect optimization

Runzi Chang, Yu Cao, Costas J. Spanos

Research output: Contribution to journal › Article › peer-review

34 Scopus citations

Abstract

A dishing model is developed to investigate the electrical effects of metal dishing in the damascene process, based on experimental data and physical analysis. A metric for dishing, the Dishing Radius, has been defined. A study utilizing this model shows that the impact of dishing on performance can be mitigated at both the process and design stages. More specifically, process improvement is most effective when the dishing radius is less than 50 μm. During design, dishing effects can be suppressed by uniformly splitting a wide line into several narrower lines; the most beneficial number of line-splitting is between two and four from both efficiency and performance considerations.

Original language	English (US)
Pages (from-to)	1577-1583
Number of pages	7
Journal	IEEE Transactions on Electron Devices
Volume	51
Issue number	10
DOIs	https://doi.org/10.1109/TED.2004.834898
State	Published - Oct 2004
Externally published	Yes

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/TED.2004.834898

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abstract = "A dishing model is developed to investigate the electrical effects of metal dishing in the damascene process, based on experimental data and physical analysis. A metric for dishing, the Dishing Radius, has been defined. A study utilizing this model shows that the impact of dishing on performance can be mitigated at both the process and design stages. More specifically, process improvement is most effective when the dishing radius is less than 50 μm. During design, dishing effects can be suppressed by uniformly splitting a wide line into several narrower lines; the most beneficial number of line-splitting is between two and four from both efficiency and performance considerations.",

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Modeling the electrical effects of metal dishing due to CMP for on-chip interconnect optimization

Abstract

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