Modeling the electrical effects of metal dishing due to CMP for on-chip interconnect optimization

Runzi Chang, Yu Cao, Costas J. Spanos

Research output: Contribution to journalArticle

21 Citations (Scopus)

Abstract

A dishing model is developed to investigate the electrical effects of metal dishing in the damascene process, based on experimental data and physical analysis. A metric for dishing, the Dishing Radius, has been defined. A study utilizing this model shows that the impact of dishing on performance can be mitigated at both the process and design stages. More specifically, process improvement is most effective when the dishing radius is less than 50 μm. During design, dishing effects can be suppressed by uniformly splitting a wide line into several narrower lines; the most beneficial number of line-splitting is between two and four from both efficiency and performance considerations.

Original languageEnglish (US)
Pages (from-to)1577-1583
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume51
Issue number10
DOIs
StatePublished - Oct 2004
Externally publishedYes

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Cytidine Monophosphate
Metals
chips
optimization
radii
metals

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Physics and Astronomy (miscellaneous)

Cite this

Modeling the electrical effects of metal dishing due to CMP for on-chip interconnect optimization. / Chang, Runzi; Cao, Yu; Spanos, Costas J.

In: IEEE Transactions on Electron Devices, Vol. 51, No. 10, 10.2004, p. 1577-1583.

Research output: Contribution to journalArticle

@article{0e813f200ceb4e8488769d7ea0eac2eb,
title = "Modeling the electrical effects of metal dishing due to CMP for on-chip interconnect optimization",
abstract = "A dishing model is developed to investigate the electrical effects of metal dishing in the damascene process, based on experimental data and physical analysis. A metric for dishing, the Dishing Radius, has been defined. A study utilizing this model shows that the impact of dishing on performance can be mitigated at both the process and design stages. More specifically, process improvement is most effective when the dishing radius is less than 50 μm. During design, dishing effects can be suppressed by uniformly splitting a wide line into several narrower lines; the most beneficial number of line-splitting is between two and four from both efficiency and performance considerations.",
author = "Runzi Chang and Yu Cao and Spanos, {Costas J.}",
year = "2004",
month = "10",
doi = "10.1109/TED.2004.834898",
language = "English (US)",
volume = "51",
pages = "1577--1583",
journal = "IEEE Transactions on Electron Devices",
issn = "0018-9383",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "10",

}

TY - JOUR

T1 - Modeling the electrical effects of metal dishing due to CMP for on-chip interconnect optimization

AU - Chang, Runzi

AU - Cao, Yu

AU - Spanos, Costas J.

PY - 2004/10

Y1 - 2004/10

N2 - A dishing model is developed to investigate the electrical effects of metal dishing in the damascene process, based on experimental data and physical analysis. A metric for dishing, the Dishing Radius, has been defined. A study utilizing this model shows that the impact of dishing on performance can be mitigated at both the process and design stages. More specifically, process improvement is most effective when the dishing radius is less than 50 μm. During design, dishing effects can be suppressed by uniformly splitting a wide line into several narrower lines; the most beneficial number of line-splitting is between two and four from both efficiency and performance considerations.

AB - A dishing model is developed to investigate the electrical effects of metal dishing in the damascene process, based on experimental data and physical analysis. A metric for dishing, the Dishing Radius, has been defined. A study utilizing this model shows that the impact of dishing on performance can be mitigated at both the process and design stages. More specifically, process improvement is most effective when the dishing radius is less than 50 μm. During design, dishing effects can be suppressed by uniformly splitting a wide line into several narrower lines; the most beneficial number of line-splitting is between two and four from both efficiency and performance considerations.

UR - http://www.scopus.com/inward/record.url?scp=5444255768&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=5444255768&partnerID=8YFLogxK

U2 - 10.1109/TED.2004.834898

DO - 10.1109/TED.2004.834898

M3 - Article

VL - 51

SP - 1577

EP - 1583

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

SN - 0018-9383

IS - 10

ER -