Abstract

In recent years, technology has advanced to fabricate integrated circuits (ICs) at 14 nm gate length commercially [1]. Fab industry giants, such as Intel, TSMC, Samsung, and Global Foundries, have plans to fabricate ICs at 10 nm by 2017. Samsung has already fabricated and tested 128 Mb SRAM in 10 nm [2] and is hoping to commercialize the process by the end of 2016. This aggressive scaling of technology is possible because of the advent of fin-shaped 2field-effect transistors (FinFETs) and fully depleted silicon-on-insulator (FD-SOI) device technology.

Original languageEnglish (US)
Title of host publicationNanophononics
Subtitle of host publicationThermal Generation, Transport, and Conversion at the Nanoscale
PublisherPan Stanford Publishing Pte. Ltd.
Pages1-30
Number of pages30
ISBN (Electronic)9781351609449
ISBN (Print)9789814774413
DOIs
StatePublished - Jan 1 2017

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ASJC Scopus subject areas

  • Physics and Astronomy(all)
  • Engineering(all)
  • Materials Science(all)

Cite this

Raleva, K., Shaik, A. R., Qazi, S. S., Daugherty, R., Laturia, A., Kaczer, B., Bury, E., & Vasileska, D. (2017). Modeling self-heating effects in nanoscale devices. In Nanophononics: Thermal Generation, Transport, and Conversion at the Nanoscale (pp. 1-30). Pan Stanford Publishing Pte. Ltd.. https://doi.org/10.1201/9781315108223