Modeling of layout-dependent stress effect in CMOS design

Chi Chao Wang, Wei Zhao, Frank Liu, Min Chen, Yu Cao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

26 Citations (Scopus)

Abstract

Strain technology has been successfully integrated into CMOS fabrication to improve carrier transport properties since 90nm node. Due to the non-uniform stress distribution in the channel, the enhancement in carrier mobility, velocity, and threshold voltage shift strongly depend on circuit layout, leading to systematic performance variations among transistors. A compact stress model that physically captures this behavior is essential to bridge the process technology with design optimization. In this paper, starting from the first principle, a new layout-dependent stress model is proposed as a function of layout, temperature, and other device parameters. Furthermore, a method of layout decomposition is developed to partition the layout into a set of simple patterns for efficient model extraction. These solutions significantly reduce the complexity in stress modeling and simulation. They are comprehensively validated by TCAD simulation and published Si-data, including the state-of-the-art strain technologies and the STI stress effect. By embedding them into circuit analysis, the interaction between layout and circuit performance is well benchmarked at 45nm node.

Original languageEnglish (US)
Title of host publicationIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
Pages513-520
Number of pages8
StatePublished - 2009
Event2009 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2009 - San Jose, CA, United States
Duration: Nov 2 2009Nov 5 2009

Other

Other2009 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2009
CountryUnited States
CitySan Jose, CA
Period11/2/0911/5/09

Fingerprint

Integrated circuit layout
Carrier transport
Carrier mobility
Electric network analysis
Threshold voltage
Transport properties
Stress concentration
Transistors
Decomposition
Fabrication
Networks (circuits)
Temperature
Design optimization

Keywords

  • Layout dependence
  • Mobility
  • Pattern decomposition
  • Stress effect
  • Stress modeling

ASJC Scopus subject areas

  • Computer Graphics and Computer-Aided Design
  • Computer Science Applications
  • Software

Cite this

Wang, C. C., Zhao, W., Liu, F., Chen, M., & Cao, Y. (2009). Modeling of layout-dependent stress effect in CMOS design. In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD (pp. 513-520). [5361246]

Modeling of layout-dependent stress effect in CMOS design. / Wang, Chi Chao; Zhao, Wei; Liu, Frank; Chen, Min; Cao, Yu.

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD. 2009. p. 513-520 5361246.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Wang, CC, Zhao, W, Liu, F, Chen, M & Cao, Y 2009, Modeling of layout-dependent stress effect in CMOS design. in IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD., 5361246, pp. 513-520, 2009 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2009, San Jose, CA, United States, 11/2/09.
Wang CC, Zhao W, Liu F, Chen M, Cao Y. Modeling of layout-dependent stress effect in CMOS design. In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD. 2009. p. 513-520. 5361246
Wang, Chi Chao ; Zhao, Wei ; Liu, Frank ; Chen, Min ; Cao, Yu. / Modeling of layout-dependent stress effect in CMOS design. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD. 2009. pp. 513-520
@inproceedings{4b54fd09042944f099213818c0a5bac7,
title = "Modeling of layout-dependent stress effect in CMOS design",
abstract = "Strain technology has been successfully integrated into CMOS fabrication to improve carrier transport properties since 90nm node. Due to the non-uniform stress distribution in the channel, the enhancement in carrier mobility, velocity, and threshold voltage shift strongly depend on circuit layout, leading to systematic performance variations among transistors. A compact stress model that physically captures this behavior is essential to bridge the process technology with design optimization. In this paper, starting from the first principle, a new layout-dependent stress model is proposed as a function of layout, temperature, and other device parameters. Furthermore, a method of layout decomposition is developed to partition the layout into a set of simple patterns for efficient model extraction. These solutions significantly reduce the complexity in stress modeling and simulation. They are comprehensively validated by TCAD simulation and published Si-data, including the state-of-the-art strain technologies and the STI stress effect. By embedding them into circuit analysis, the interaction between layout and circuit performance is well benchmarked at 45nm node.",
keywords = "Layout dependence, Mobility, Pattern decomposition, Stress effect, Stress modeling",
author = "Wang, {Chi Chao} and Wei Zhao and Frank Liu and Min Chen and Yu Cao",
year = "2009",
language = "English (US)",
isbn = "9781605588001",
pages = "513--520",
booktitle = "IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD",

}

TY - GEN

T1 - Modeling of layout-dependent stress effect in CMOS design

AU - Wang, Chi Chao

AU - Zhao, Wei

AU - Liu, Frank

AU - Chen, Min

AU - Cao, Yu

PY - 2009

Y1 - 2009

N2 - Strain technology has been successfully integrated into CMOS fabrication to improve carrier transport properties since 90nm node. Due to the non-uniform stress distribution in the channel, the enhancement in carrier mobility, velocity, and threshold voltage shift strongly depend on circuit layout, leading to systematic performance variations among transistors. A compact stress model that physically captures this behavior is essential to bridge the process technology with design optimization. In this paper, starting from the first principle, a new layout-dependent stress model is proposed as a function of layout, temperature, and other device parameters. Furthermore, a method of layout decomposition is developed to partition the layout into a set of simple patterns for efficient model extraction. These solutions significantly reduce the complexity in stress modeling and simulation. They are comprehensively validated by TCAD simulation and published Si-data, including the state-of-the-art strain technologies and the STI stress effect. By embedding them into circuit analysis, the interaction between layout and circuit performance is well benchmarked at 45nm node.

AB - Strain technology has been successfully integrated into CMOS fabrication to improve carrier transport properties since 90nm node. Due to the non-uniform stress distribution in the channel, the enhancement in carrier mobility, velocity, and threshold voltage shift strongly depend on circuit layout, leading to systematic performance variations among transistors. A compact stress model that physically captures this behavior is essential to bridge the process technology with design optimization. In this paper, starting from the first principle, a new layout-dependent stress model is proposed as a function of layout, temperature, and other device parameters. Furthermore, a method of layout decomposition is developed to partition the layout into a set of simple patterns for efficient model extraction. These solutions significantly reduce the complexity in stress modeling and simulation. They are comprehensively validated by TCAD simulation and published Si-data, including the state-of-the-art strain technologies and the STI stress effect. By embedding them into circuit analysis, the interaction between layout and circuit performance is well benchmarked at 45nm node.

KW - Layout dependence

KW - Mobility

KW - Pattern decomposition

KW - Stress effect

KW - Stress modeling

UR - http://www.scopus.com/inward/record.url?scp=76349094452&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=76349094452&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:76349094452

SN - 9781605588001

SP - 513

EP - 520

BT - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

ER -