TY - GEN
T1 - Modeling of layout-dependent stress effect in CMOS design
AU - Wang, Chi Chao
AU - Zhao, Wei
AU - Liu, Frank
AU - Chen, Min
AU - Cao, Yu
PY - 2009
Y1 - 2009
N2 - Strain technology has been successfully integrated into CMOS fabrication to improve carrier transport properties since 90nm node. Due to the non-uniform stress distribution in the channel, the enhancement in carrier mobility, velocity, and threshold voltage shift strongly depend on circuit layout, leading to systematic performance variations among transistors. A compact stress model that physically captures this behavior is essential to bridge the process technology with design optimization. In this paper, starting from the first principle, a new layout-dependent stress model is proposed as a function of layout, temperature, and other device parameters. Furthermore, a method of layout decomposition is developed to partition the layout into a set of simple patterns for efficient model extraction. These solutions significantly reduce the complexity in stress modeling and simulation. They are comprehensively validated by TCAD simulation and published Si-data, including the state-of-the-art strain technologies and the STI stress effect. By embedding them into circuit analysis, the interaction between layout and circuit performance is well benchmarked at 45nm node.
AB - Strain technology has been successfully integrated into CMOS fabrication to improve carrier transport properties since 90nm node. Due to the non-uniform stress distribution in the channel, the enhancement in carrier mobility, velocity, and threshold voltage shift strongly depend on circuit layout, leading to systematic performance variations among transistors. A compact stress model that physically captures this behavior is essential to bridge the process technology with design optimization. In this paper, starting from the first principle, a new layout-dependent stress model is proposed as a function of layout, temperature, and other device parameters. Furthermore, a method of layout decomposition is developed to partition the layout into a set of simple patterns for efficient model extraction. These solutions significantly reduce the complexity in stress modeling and simulation. They are comprehensively validated by TCAD simulation and published Si-data, including the state-of-the-art strain technologies and the STI stress effect. By embedding them into circuit analysis, the interaction between layout and circuit performance is well benchmarked at 45nm node.
KW - Layout dependence
KW - Mobility
KW - Pattern decomposition
KW - Stress effect
KW - Stress modeling
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U2 - 10.1145/1687399.1687496
DO - 10.1145/1687399.1687496
M3 - Conference contribution
AN - SCOPUS:76349094452
SN - 9781605588001
T3 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
SP - 513
EP - 520
BT - Proceedings of the 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers, ICCAD 2009
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2009 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2009
Y2 - 2 November 2009 through 5 November 2009
ER -