Modeling of dynamic threshold voltage of high K gate stack and application in FinFET reliability simulation

Yun Ye; Hongyu He; Chenyue Ma; Cheng Wang; Aixi Zhang; Jin He; Yu Cao

Modeling of dynamic threshold voltage of high K gate stack and application in FinFET reliability simulation

Yun Ye, Hongyu He, Chenyue Ma, Cheng Wang, Aixi Zhang, Jin He, Yu Cao

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A modeling study of dynamic threshold voltage in high K gate stack is reported in this paper. Both slow transient (STCE) and fast transient charging effect (FTCE) are included in this model. Finally, this model is applied in FinFET reliability and circuit performances are simulated. The result shows that, the drain circuit (IJ) degradation in FinFET is much more obvious than normal MOSFETs with the same processes and the variation of I _d is slower in higher temperature. However, the dynamic threshold voltage in high K stack seems not affect the delay time of reverser simulated by HSPICE.

Original language	English (US)
Title of host publication	Nanotechnology 2012
Subtitle of host publication	Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2012 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2012
Pages	428-431
Number of pages	4
State	Published - 2012
Externally published	Yes
Event	Nanotechnology 2012: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2012 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2012 - Santa Clara, CA, United States Duration: Jun 18 2012 → Jun 21 2012

Publication series

Name	Technical Proceedings of the 2012 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2012

Other

Other	Nanotechnology 2012: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2012 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2012
Country/Territory	United States
City	Santa Clara, CA
Period	6/18/12 → 6/21/12

ASJC Scopus subject areas

Ceramics and Composites
Surfaces, Coatings and Films

Cite this

Ye, Y., He, H., Ma, C., Wang, C., Zhang, A., He, J., & Cao, Y. (2012). Modeling of dynamic threshold voltage of high K gate stack and application in FinFET reliability simulation. In Nanotechnology 2012: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2012 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2012 (pp. 428-431). (Technical Proceedings of the 2012 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2012).

Modeling of dynamic threshold voltage of high K gate stack and application in FinFET reliability simulation. / Ye, Yun; He, Hongyu; Ma, Chenyue et al.
Nanotechnology 2012: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2012 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2012. 2012. p. 428-431 (Technical Proceedings of the 2012 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2012).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ye, Y, He, H, Ma, C, Wang, C, Zhang, A, He, J & Cao, Y 2012, Modeling of dynamic threshold voltage of high K gate stack and application in FinFET reliability simulation. in Nanotechnology 2012: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2012 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2012. Technical Proceedings of the 2012 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2012, pp. 428-431, Nanotechnology 2012: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2012 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2012, Santa Clara, CA, United States, 6/18/12.

Ye Y, He H, Ma C, Wang C, Zhang A, He J et al. Modeling of dynamic threshold voltage of high K gate stack and application in FinFET reliability simulation. In Nanotechnology 2012: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2012 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2012. 2012. p. 428-431. (Technical Proceedings of the 2012 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2012).

Ye, Yun ; He, Hongyu ; Ma, Chenyue et al. / Modeling of dynamic threshold voltage of high K gate stack and application in FinFET reliability simulation. Nanotechnology 2012: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2012 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2012. 2012. pp. 428-431 (Technical Proceedings of the 2012 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2012).

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abstract = "A modeling study of dynamic threshold voltage in high K gate stack is reported in this paper. Both slow transient (STCE) and fast transient charging effect (FTCE) are included in this model. Finally, this model is applied in FinFET reliability and circuit performances are simulated. The result shows that, the drain circuit (IJ) degradation in FinFET is much more obvious than normal MOSFETs with the same processes and the variation of I d is slower in higher temperature. However, the dynamic threshold voltage in high K stack seems not affect the delay time of reverser simulated by HSPICE.",

author = "Yun Ye and Hongyu He and Chenyue Ma and Cheng Wang and Aixi Zhang and Jin He and Yu Cao",

note = "Copyright: Copyright 2012 Elsevier B.V., All rights reserved.; Nanotechnology 2012: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2012 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2012 ; Conference date: 18-06-2012 Through 21-06-2012",

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AU - Ye, Yun

AU - He, Hongyu

AU - Ma, Chenyue

AU - Wang, Cheng

AU - Zhang, Aixi

AU - He, Jin

AU - Cao, Yu

PY - 2012

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AB - A modeling study of dynamic threshold voltage in high K gate stack is reported in this paper. Both slow transient (STCE) and fast transient charging effect (FTCE) are included in this model. Finally, this model is applied in FinFET reliability and circuit performances are simulated. The result shows that, the drain circuit (IJ) degradation in FinFET is much more obvious than normal MOSFETs with the same processes and the variation of I d is slower in higher temperature. However, the dynamic threshold voltage in high K stack seems not affect the delay time of reverser simulated by HSPICE.

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ER -

Modeling of dynamic threshold voltage of high K gate stack and application in FinFET reliability simulation

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