Modeling of dynamic threshold voltage of high K gate stack and application in FinFET reliability simulation

Yun Ye, Hongyu He, Chenyue Ma, Cheng Wang, Aixi Zhang, Jin He, Yu Cao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A modeling study of dynamic threshold voltage in high K gate stack is reported in this paper. Both slow transient (STCE) and fast transient charging effect (FTCE) are included in this model. Finally, this model is applied in FinFET reliability and circuit performances are simulated. The result shows that, the drain circuit (IJ) degradation in FinFET is much more obvious than normal MOSFETs with the same processes and the variation of I d is slower in higher temperature. However, the dynamic threshold voltage in high K stack seems not affect the delay time of reverser simulated by HSPICE.

Original languageEnglish (US)
Title of host publicationNanotechnology 2012
Subtitle of host publicationElectronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2012 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2012
Pages428-431
Number of pages4
StatePublished - 2012
Externally publishedYes
EventNanotechnology 2012: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2012 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2012 - Santa Clara, CA, United States
Duration: Jun 18 2012Jun 21 2012

Publication series

NameTechnical Proceedings of the 2012 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2012

Other

OtherNanotechnology 2012: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2012 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2012
CountryUnited States
CitySanta Clara, CA
Period6/18/126/21/12

ASJC Scopus subject areas

  • Ceramics and Composites
  • Surfaces, Coatings and Films

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