Modeling Metal Dishing for Interconnect Optimization

Runzi Chang, Yu Cao, Costas J. Spanos

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

An analytical dishing model is developed for the damascene process, based on experimental data and physical analysis. A study utilizing this model shows that the impact of dishing on performance can be mitigated at both the process and design stages. More specifically, process improvement is favorable when the dishing radius is less than 50μm. During design, dishing effects can be suppressed by uniformly splitting a wide line into several narrower lines; the most beneficial number of line-splitting is 2-4 from both efficiency and performance considerations.

Original languageEnglish (US)
Title of host publicationTechnical Digest - International Electron Devices Meeting
Pages249-252
Number of pages4
StatePublished - 2003
Externally publishedYes
EventIEEE International Electron Devices Meeting - Washington, DC, United States
Duration: Dec 8 2003Dec 10 2003

Other

OtherIEEE International Electron Devices Meeting
CountryUnited States
CityWashington, DC
Period12/8/0312/10/03

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Chang, R., Cao, Y., & Spanos, C. J. (2003). Modeling Metal Dishing for Interconnect Optimization. In Technical Digest - International Electron Devices Meeting (pp. 249-252)