Abstract
An analytical dishing model is developed for the damascene process, based on experimental data and physical analysis. A study utilizing this model shows that the impact of dishing on performance can be mitigated at both the process and design stages. More specifically, process improvement is favorable when the dishing radius is less than 50μm. During design, dishing effects can be suppressed by uniformly splitting a wide line into several narrower lines; the most beneficial number of line-splitting is 2-4 from both efficiency and performance considerations.
| Original language | English (US) |
|---|---|
| Title of host publication | Technical Digest - International Electron Devices Meeting |
| Pages | 249-252 |
| Number of pages | 4 |
| State | Published - 2003 |
| Externally published | Yes |
| Event | IEEE International Electron Devices Meeting - Washington, DC, United States Duration: Dec 8 2003 → Dec 10 2003 |
Other
| Other | IEEE International Electron Devices Meeting |
|---|---|
| Country/Territory | United States |
| City | Washington, DC |
| Period | 12/8/03 → 12/10/03 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering