We utilize a fully quantum mechanical transport simulator based on the Contact Block Reduction (CBR) method to investigate the influence of interface roughness in nanoscale FinFET devices. In this work we treat interface roughness by creating a random deviation at ideal Si/SiO2 interface in real space, and then solving quantum transport problem fully self-consistently with the gates for the resulting device potential. We study the influence of interface roughness on device capacitance, drain current, and gate leakage for different regime of operation. Our simulation results show that gate leakage is significantly affected by surface roughness, even though the average oxide thickness remains approximately the same. On the other hand, the on-current is comparatively less sensitive to the interface roughness for FinFET devices with narrow fin width. Furthermore, we And that interface roughness significantly affects both the intrinsic switching speed and, especially, the cut-off frequency of FinFET with narrow fin thickness.