Modeling and analysis of the nonrectangular gate effect for postlithography circuit simulation

Ritu Singal, Asha Balijepalli, Anupama Subramaniam, Chi Chao Wang, Frank Liu, Sani R. Nassif, Yu Cao

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

For nanoscale CMOS devices, gate roughness has severe impact on the device I-V characteristics, particularly in the subthreshold region. In particular, the nonrectangular gate (NRG) geometries are caused by subwavelength lithography and have relatively low spatial frequency. In this paper, we present an analytical approach to model NRG effects on I-V characteristics. To predict the change of I-V characteristics due to the NRG effect, the proposed model converts the postlithography gate profile into an equivalent gate length Le, which is a function of the gate bias voltage but independent of the drain bias voltage. We demonstrate the accuracy of this approach by comparing it to TCAD simulation results for 65-nm technology. The new Le model is readily integrated into standard transistor models in traditional circuit simulation tools, such as SPICE, for both dc and transient analyses. We further develop a generic procedure to systematically extract the Le value from the postlithography gate profile. The interaction with the narrow-width effect is also efficiently incorporated into the proposed algorithm. TCAD verification demonstrates that the proposed Le model is simple for implementation, scalable with both transistor geometries and bias conditions, and also continuous across all the operation regions.

Original languageEnglish (US)
Article number5153589
Pages (from-to)666-670
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume18
Issue number4
DOIs
StatePublished - Apr 2010

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Circuit simulation
Bias voltage
Transistors
Geometry
SPICE
Lithography
Surface roughness

Keywords

  • Equivalent gate length (EGL)
  • Leakage
  • Line-edge roughness (LER)
  • Narrow-width effect (NWE)
  • Nonrectangular gate (NRG)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Software

Cite this

Modeling and analysis of the nonrectangular gate effect for postlithography circuit simulation. / Singal, Ritu; Balijepalli, Asha; Subramaniam, Anupama; Wang, Chi Chao; Liu, Frank; Nassif, Sani R.; Cao, Yu.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 18, No. 4, 5153589, 04.2010, p. 666-670.

Research output: Contribution to journalArticle

Singal, Ritu ; Balijepalli, Asha ; Subramaniam, Anupama ; Wang, Chi Chao ; Liu, Frank ; Nassif, Sani R. ; Cao, Yu. / Modeling and analysis of the nonrectangular gate effect for postlithography circuit simulation. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2010 ; Vol. 18, No. 4. pp. 666-670.
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