Modeling and analysis of non-rectangular gate for post-lithography circuit simulation

Ritu Singhal, Asha Balijepalli, Anupama Subramaniam, Frank Liu, Sani Nassif, Yu Cao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

47 Citations (Scopus)

Abstract

In the nano regime it has become increasingly important to consider the impact of non-rectangular gate (NRG) shape caused due to sub-wavelength lithography. NRG dramatically increases the leakage current and requires geometry dependent transistor models for post-litho circuit simulation. In this paper, we propose a coherent modeling approach for non-rectangular gates based on equivalent gate length (L e). A gate-voltage dependent model of L e is developed which is scalable with design conditions, continuous across weak and strong inversion regions, accurate for both leakage and saturation current, and compatible with standard circuit analysis tools. We systematically verify this approach with 65nm TCAD simulations. A generic CAD algorithm is further proposed to predict the value of L e under various non-rectangular geometries. The interaction with the narrow-width effect is efficiently convolved in this method. Depending on the gate geometry, the leakage current can vary more than 15X at 65nm technology node. Our analytical method well captures this effect. Finally, we extrapolate the impact of NRG effect on future technology generations. The proposed model can be easily extracted from TCAD tools or direct silicon data. It bridges the gap between lithography, simulation, and circuit analysis for measuring transistor performance under increasingly severe NRG effect.

Original languageEnglish (US)
Title of host publicationProceedings - Design Automation Conference
Pages823-828
Number of pages6
DOIs
StatePublished - 2007
Event2007 44th ACM/IEEE Design Automation Conference, DAC'07 - San Diego, CA, United States
Duration: Jun 4 2007Jun 8 2007

Other

Other2007 44th ACM/IEEE Design Automation Conference, DAC'07
CountryUnited States
CitySan Diego, CA
Period6/4/076/8/07

Fingerprint

Circuit simulation
Lithography
Electric network analysis
Leakage currents
Geometry
Transistors
Computer aided design
Silicon
Wavelength
Electric potential

Keywords

  • Compact modeling
  • Equivalent gate length
  • Leakage
  • Narrow-width effect
  • Non-rectangular gate

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering

Cite this

Singhal, R., Balijepalli, A., Subramaniam, A., Liu, F., Nassif, S., & Cao, Y. (2007). Modeling and analysis of non-rectangular gate for post-lithography circuit simulation. In Proceedings - Design Automation Conference (pp. 823-828). [4261297] https://doi.org/10.1109/DAC.2007.375278

Modeling and analysis of non-rectangular gate for post-lithography circuit simulation. / Singhal, Ritu; Balijepalli, Asha; Subramaniam, Anupama; Liu, Frank; Nassif, Sani; Cao, Yu.

Proceedings - Design Automation Conference. 2007. p. 823-828 4261297.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Singhal, R, Balijepalli, A, Subramaniam, A, Liu, F, Nassif, S & Cao, Y 2007, Modeling and analysis of non-rectangular gate for post-lithography circuit simulation. in Proceedings - Design Automation Conference., 4261297, pp. 823-828, 2007 44th ACM/IEEE Design Automation Conference, DAC'07, San Diego, CA, United States, 6/4/07. https://doi.org/10.1109/DAC.2007.375278
Singhal R, Balijepalli A, Subramaniam A, Liu F, Nassif S, Cao Y. Modeling and analysis of non-rectangular gate for post-lithography circuit simulation. In Proceedings - Design Automation Conference. 2007. p. 823-828. 4261297 https://doi.org/10.1109/DAC.2007.375278
Singhal, Ritu ; Balijepalli, Asha ; Subramaniam, Anupama ; Liu, Frank ; Nassif, Sani ; Cao, Yu. / Modeling and analysis of non-rectangular gate for post-lithography circuit simulation. Proceedings - Design Automation Conference. 2007. pp. 823-828
@inproceedings{9306a60be99f4b59bc7d6c80bbac318b,
title = "Modeling and analysis of non-rectangular gate for post-lithography circuit simulation",
abstract = "In the nano regime it has become increasingly important to consider the impact of non-rectangular gate (NRG) shape caused due to sub-wavelength lithography. NRG dramatically increases the leakage current and requires geometry dependent transistor models for post-litho circuit simulation. In this paper, we propose a coherent modeling approach for non-rectangular gates based on equivalent gate length (L e). A gate-voltage dependent model of L e is developed which is scalable with design conditions, continuous across weak and strong inversion regions, accurate for both leakage and saturation current, and compatible with standard circuit analysis tools. We systematically verify this approach with 65nm TCAD simulations. A generic CAD algorithm is further proposed to predict the value of L e under various non-rectangular geometries. The interaction with the narrow-width effect is efficiently convolved in this method. Depending on the gate geometry, the leakage current can vary more than 15X at 65nm technology node. Our analytical method well captures this effect. Finally, we extrapolate the impact of NRG effect on future technology generations. The proposed model can be easily extracted from TCAD tools or direct silicon data. It bridges the gap between lithography, simulation, and circuit analysis for measuring transistor performance under increasingly severe NRG effect.",
keywords = "Compact modeling, Equivalent gate length, Leakage, Narrow-width effect, Non-rectangular gate",
author = "Ritu Singhal and Asha Balijepalli and Anupama Subramaniam and Frank Liu and Sani Nassif and Yu Cao",
year = "2007",
doi = "10.1109/DAC.2007.375278",
language = "English (US)",
isbn = "1595936270",
pages = "823--828",
booktitle = "Proceedings - Design Automation Conference",

}

TY - GEN

T1 - Modeling and analysis of non-rectangular gate for post-lithography circuit simulation

AU - Singhal, Ritu

AU - Balijepalli, Asha

AU - Subramaniam, Anupama

AU - Liu, Frank

AU - Nassif, Sani

AU - Cao, Yu

PY - 2007

Y1 - 2007

N2 - In the nano regime it has become increasingly important to consider the impact of non-rectangular gate (NRG) shape caused due to sub-wavelength lithography. NRG dramatically increases the leakage current and requires geometry dependent transistor models for post-litho circuit simulation. In this paper, we propose a coherent modeling approach for non-rectangular gates based on equivalent gate length (L e). A gate-voltage dependent model of L e is developed which is scalable with design conditions, continuous across weak and strong inversion regions, accurate for both leakage and saturation current, and compatible with standard circuit analysis tools. We systematically verify this approach with 65nm TCAD simulations. A generic CAD algorithm is further proposed to predict the value of L e under various non-rectangular geometries. The interaction with the narrow-width effect is efficiently convolved in this method. Depending on the gate geometry, the leakage current can vary more than 15X at 65nm technology node. Our analytical method well captures this effect. Finally, we extrapolate the impact of NRG effect on future technology generations. The proposed model can be easily extracted from TCAD tools or direct silicon data. It bridges the gap between lithography, simulation, and circuit analysis for measuring transistor performance under increasingly severe NRG effect.

AB - In the nano regime it has become increasingly important to consider the impact of non-rectangular gate (NRG) shape caused due to sub-wavelength lithography. NRG dramatically increases the leakage current and requires geometry dependent transistor models for post-litho circuit simulation. In this paper, we propose a coherent modeling approach for non-rectangular gates based on equivalent gate length (L e). A gate-voltage dependent model of L e is developed which is scalable with design conditions, continuous across weak and strong inversion regions, accurate for both leakage and saturation current, and compatible with standard circuit analysis tools. We systematically verify this approach with 65nm TCAD simulations. A generic CAD algorithm is further proposed to predict the value of L e under various non-rectangular geometries. The interaction with the narrow-width effect is efficiently convolved in this method. Depending on the gate geometry, the leakage current can vary more than 15X at 65nm technology node. Our analytical method well captures this effect. Finally, we extrapolate the impact of NRG effect on future technology generations. The proposed model can be easily extracted from TCAD tools or direct silicon data. It bridges the gap between lithography, simulation, and circuit analysis for measuring transistor performance under increasingly severe NRG effect.

KW - Compact modeling

KW - Equivalent gate length

KW - Leakage

KW - Narrow-width effect

KW - Non-rectangular gate

UR - http://www.scopus.com/inward/record.url?scp=34547287531&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=34547287531&partnerID=8YFLogxK

U2 - 10.1109/DAC.2007.375278

DO - 10.1109/DAC.2007.375278

M3 - Conference contribution

SN - 1595936270

SN - 9781595936271

SP - 823

EP - 828

BT - Proceedings - Design Automation Conference

ER -