Abstract
In the nano regime it has become increasingly important to consider the impact of non-rectangular gate (NRG) shape caused due to sub-wavelength lithography. NRG dramatically increases the leakage current and requires geometry dependent transistor models for post-litho circuit simulation. In this paper, we propose a coherent modeling approach for non-rectangular gates based on equivalent gate length (L e). A gate-voltage dependent model of L e is developed which is scalable with design conditions, continuous across weak and strong inversion regions, accurate for both leakage and saturation current, and compatible with standard circuit analysis tools. We systematically verify this approach with 65nm TCAD simulations. A generic CAD algorithm is further proposed to predict the value of L e under various non-rectangular geometries. The interaction with the narrow-width effect is efficiently convolved in this method. Depending on the gate geometry, the leakage current can vary more than 15X at 65nm technology node. Our analytical method well captures this effect. Finally, we extrapolate the impact of NRG effect on future technology generations. The proposed model can be easily extracted from TCAD tools or direct silicon data. It bridges the gap between lithography, simulation, and circuit analysis for measuring transistor performance under increasingly severe NRG effect.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings - Design Automation Conference |
| Pages | 823-828 |
| Number of pages | 6 |
| DOIs | |
| State | Published - 2007 |
| Event | 2007 44th ACM/IEEE Design Automation Conference, DAC'07 - San Diego, CA, United States Duration: Jun 4 2007 → Jun 8 2007 |
Other
| Other | 2007 44th ACM/IEEE Design Automation Conference, DAC'07 |
|---|---|
| Country | United States |
| City | San Diego, CA |
| Period | 6/4/07 → 6/8/07 |
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Keywords
- Compact modeling
- Equivalent gate length
- Leakage
- Narrow-width effect
- Non-rectangular gate
ASJC Scopus subject areas
- Hardware and Architecture
- Control and Systems Engineering
Cite this
Modeling and analysis of non-rectangular gate for post-lithography circuit simulation. / Singhal, Ritu; Balijepalli, Asha; Subramaniam, Anupama; Liu, Frank; Nassif, Sani; Cao, Yu.
Proceedings - Design Automation Conference. 2007. p. 823-828 4261297.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Modeling and analysis of non-rectangular gate for post-lithography circuit simulation
AU - Singhal, Ritu
AU - Balijepalli, Asha
AU - Subramaniam, Anupama
AU - Liu, Frank
AU - Nassif, Sani
AU - Cao, Yu
PY - 2007
Y1 - 2007
N2 - In the nano regime it has become increasingly important to consider the impact of non-rectangular gate (NRG) shape caused due to sub-wavelength lithography. NRG dramatically increases the leakage current and requires geometry dependent transistor models for post-litho circuit simulation. In this paper, we propose a coherent modeling approach for non-rectangular gates based on equivalent gate length (L e). A gate-voltage dependent model of L e is developed which is scalable with design conditions, continuous across weak and strong inversion regions, accurate for both leakage and saturation current, and compatible with standard circuit analysis tools. We systematically verify this approach with 65nm TCAD simulations. A generic CAD algorithm is further proposed to predict the value of L e under various non-rectangular geometries. The interaction with the narrow-width effect is efficiently convolved in this method. Depending on the gate geometry, the leakage current can vary more than 15X at 65nm technology node. Our analytical method well captures this effect. Finally, we extrapolate the impact of NRG effect on future technology generations. The proposed model can be easily extracted from TCAD tools or direct silicon data. It bridges the gap between lithography, simulation, and circuit analysis for measuring transistor performance under increasingly severe NRG effect.
AB - In the nano regime it has become increasingly important to consider the impact of non-rectangular gate (NRG) shape caused due to sub-wavelength lithography. NRG dramatically increases the leakage current and requires geometry dependent transistor models for post-litho circuit simulation. In this paper, we propose a coherent modeling approach for non-rectangular gates based on equivalent gate length (L e). A gate-voltage dependent model of L e is developed which is scalable with design conditions, continuous across weak and strong inversion regions, accurate for both leakage and saturation current, and compatible with standard circuit analysis tools. We systematically verify this approach with 65nm TCAD simulations. A generic CAD algorithm is further proposed to predict the value of L e under various non-rectangular geometries. The interaction with the narrow-width effect is efficiently convolved in this method. Depending on the gate geometry, the leakage current can vary more than 15X at 65nm technology node. Our analytical method well captures this effect. Finally, we extrapolate the impact of NRG effect on future technology generations. The proposed model can be easily extracted from TCAD tools or direct silicon data. It bridges the gap between lithography, simulation, and circuit analysis for measuring transistor performance under increasingly severe NRG effect.
KW - Compact modeling
KW - Equivalent gate length
KW - Leakage
KW - Narrow-width effect
KW - Non-rectangular gate
UR - http://www.scopus.com/inward/record.url?scp=34547287531&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=34547287531&partnerID=8YFLogxK
U2 - 10.1109/DAC.2007.375278
DO - 10.1109/DAC.2007.375278
M3 - Conference contribution
AN - SCOPUS:34547287531
SN - 1595936270
SN - 9781595936271
SP - 823
EP - 828
BT - Proceedings - Design Automation Conference
ER -