TY - GEN
T1 - Mitigating the effect of reliability soft-errors of RRAM devices on the performance of RRAM-based neuromorphic systems
AU - Tosson, Amr M.S.
AU - Yu, Shimeng
AU - Anis, Mohab
AU - Wei, Lan
N1 - Publisher Copyright:
© 2017 ACM.
PY - 2017/5/10
Y1 - 2017/5/10
N2 - With the speed and power bottleneck in the conventional Von Neumann architecture, the interest in the neuromorphic systems has greatly increased in recent years. To create a highly dense communication network between the preand post-neurons, RRAM devices are used as synapses in the neuromorphic systems due to many advantages including their small sizes and low-power operations. However, due to RRAM reliability issues, in particular soft-errors, the performance of the RRAM-based neuromorphic systems are significantly degraded. In this article, we propose a novel framework for detecting and resolving the degradation in the system performance due to the RRAM reliability soft-errors. The read and write circuits modifications to implement the framework, and their impact on the delay and energy consumption of the neuromorphic system are also discussed in this article. Using a combination of BRIAN and SPICE simulations, we demonstrate that the proposed framework can restore the accuracy of the example RRAM-based neuromorphic system from 43% back to its target value of 91.6% with a minimal impact on the read (< 0.1% and 1.1% increase in the delay and energy respectively) and write (0% and < 0.1% increase in the delay and energy respectively) operations.
AB - With the speed and power bottleneck in the conventional Von Neumann architecture, the interest in the neuromorphic systems has greatly increased in recent years. To create a highly dense communication network between the preand post-neurons, RRAM devices are used as synapses in the neuromorphic systems due to many advantages including their small sizes and low-power operations. However, due to RRAM reliability issues, in particular soft-errors, the performance of the RRAM-based neuromorphic systems are significantly degraded. In this article, we propose a novel framework for detecting and resolving the degradation in the system performance due to the RRAM reliability soft-errors. The read and write circuits modifications to implement the framework, and their impact on the delay and energy consumption of the neuromorphic system are also discussed in this article. Using a combination of BRIAN and SPICE simulations, we demonstrate that the proposed framework can restore the accuracy of the example RRAM-based neuromorphic system from 43% back to its target value of 91.6% with a minimal impact on the read (< 0.1% and 1.1% increase in the delay and energy respectively) and write (0% and < 0.1% increase in the delay and energy respectively) operations.
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U2 - 10.1145/3060403.3060431
DO - 10.1145/3060403.3060431
M3 - Conference contribution
AN - SCOPUS:85021194696
T3 - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
SP - 53
EP - 58
BT - GLSVLSI 2017 - Proceedings of the Great Lakes Symposium on VLSI 2017
PB - Association for Computing Machinery
T2 - 27th Great Lakes Symposium on VLSI, GLSVLSI 2017
Y2 - 10 May 2017 through 12 May 2017
ER -