Minimizing total weighted tardiness on a single batch process machine with incompatible job families

Imelda C. Perez, John Fowler, W. Matthew Carlyle

Research output: Contribution to journalArticlepeer-review

76 Scopus citations

Abstract

The diffusion step in semiconductor wafer fabrication is very time consuming, compared to other steps in the process, and performance in this area has a significant impact on overall factory performance. Diffusion furnaces are able to process multiple lots of similar wafers at a time, and are therefore appropriately modeled as batch processing machines with incompatible job families. Due to the importance of on-time delivery in semiconductor manufacturing, we focus on minimizing the total weighted tardiness in this environment. The resulting problem is NP-Hard, and we decompose it into two sequential decision problems: assigning lots to batches followed by sequencing the batches. We develop several heuristics for these subproblems and test their performance.

Original languageEnglish (US)
Pages (from-to)327-341
Number of pages15
JournalComputers and Operations Research
Volume32
Issue number2
DOIs
StatePublished - Feb 1 2005

ASJC Scopus subject areas

  • Computer Science(all)
  • Modeling and Simulation
  • Management Science and Operations Research

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