Minimizing total weighted tardiness on a single batch process machine with incompatible job families

Imelda C. Perez, John Fowler, W. Matthew Carlyle

Research output: Contribution to journalArticle

71 Citations (Scopus)

Abstract

The diffusion step in semiconductor wafer fabrication is very time consuming, compared to other steps in the process, and performance in this area has a significant impact on overall factory performance. Diffusion furnaces are able to process multiple lots of similar wafers at a time, and are therefore appropriately modeled as batch processing machines with incompatible job families. Due to the importance of on-time delivery in semiconductor manufacturing, we focus on minimizing the total weighted tardiness in this environment. The resulting problem is NP-Hard, and we decompose it into two sequential decision problems: assigning lots to batches followed by sequencing the batches. We develop several heuristics for these subproblems and test their performance.

Original languageEnglish (US)
Pages (from-to)327-341
Number of pages15
JournalComputers and Operations Research
Volume32
Issue number2
DOIs
StatePublished - Feb 2005

Fingerprint

Batch Process
Tardiness
Semiconductor materials
Wafer
Batch
Batch Processing Machine
performance
Industrial plants
Computational complexity
Semiconductor Manufacturing
Furnaces
Performance Test
Furnace
factory
Decision problem
Fabrication
Sequencing
Semiconductors
heuristics
manufacturing

ASJC Scopus subject areas

  • Information Systems and Management
  • Management Science and Operations Research
  • Applied Mathematics
  • Modeling and Simulation
  • Transportation

Cite this

Minimizing total weighted tardiness on a single batch process machine with incompatible job families. / Perez, Imelda C.; Fowler, John; Carlyle, W. Matthew.

In: Computers and Operations Research, Vol. 32, No. 2, 02.2005, p. 327-341.

Research output: Contribution to journalArticle

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