Dynamically reconfigurable computing systems built on FPGAs offer a variety of benefits; however, the reconfiguration cost in terms of power dissipation and delay in such systems is the key negative factor limiting system performance. We describe a hardware organization that allows for simple dynamic placement and routing through introduction of a virtual standard cell topology over an FPGA. We focus on the channel routing issues under the assumption that the FPGA hardware is partially (selectively) reconfigurable. Even though the channel capacity is fixed, routes that cannot fit in the channel at once can share the reconfigurable channel over time. The cost of configuring a new routing pattern can be greatly reduced if portions of the last configured routing pattern are reused. We address the problem of minimization of the configuration cost through maximization of the reuse of an already existing configuration of the channel.