Minimizing routing configuration cost in dynamically reconfigurable FPGAs

D. Rakhmatov, Sarma Vrudhula

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

Dynamically reconfigurable computing systems built on FPGAs offer a variety of benefits; however, the reconfiguration cost in terms of power dissipation and delay in such systems is the key negative factor limiting system performance. We describe a hardware organization that allows for simple dynamic placement and routing through introduction of a virtual standard cell topology over an FPGA. We focus on the channel routing issues under the assumption that the FPGA hardware is partially (selectively) reconfigurable. Even though the channel capacity is fixed, routes that cannot fit in the channel at once can share the reconfigurable channel over time. The cost of configuring a new routing pattern can be greatly reduced if portions of the last configured routing pattern are reused. We address the problem of minimization of the configuration cost through maximization of the reuse of an already existing configuration of the channel.

Original languageEnglish (US)
Title of host publicationProceedings - 15th International Parallel and Distributed Processing Symposium, IPDPS 2001
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1481-1488
Number of pages8
ISBN (Electronic)0769509908, 9780769509907
DOIs
StatePublished - 2001
Event15th International Parallel and Distributed Processing Symposium, IPDPS 2001 - San Francisco, United States
Duration: Apr 23 2001Apr 27 2001

Other

Other15th International Parallel and Distributed Processing Symposium, IPDPS 2001
CountryUnited States
CitySan Francisco
Period4/23/014/27/01

Fingerprint

Field programmable gate arrays (FPGA)
Hardware
Costs
Channel capacity
Energy dissipation
Topology

ASJC Scopus subject areas

  • Hardware and Architecture
  • Computer Networks and Communications

Cite this

Rakhmatov, D., & Vrudhula, S. (2001). Minimizing routing configuration cost in dynamically reconfigurable FPGAs. In Proceedings - 15th International Parallel and Distributed Processing Symposium, IPDPS 2001 (pp. 1481-1488). [925132] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IPDPS.2001.925132

Minimizing routing configuration cost in dynamically reconfigurable FPGAs. / Rakhmatov, D.; Vrudhula, Sarma.

Proceedings - 15th International Parallel and Distributed Processing Symposium, IPDPS 2001. Institute of Electrical and Electronics Engineers Inc., 2001. p. 1481-1488 925132.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Rakhmatov, D & Vrudhula, S 2001, Minimizing routing configuration cost in dynamically reconfigurable FPGAs. in Proceedings - 15th International Parallel and Distributed Processing Symposium, IPDPS 2001., 925132, Institute of Electrical and Electronics Engineers Inc., pp. 1481-1488, 15th International Parallel and Distributed Processing Symposium, IPDPS 2001, San Francisco, United States, 4/23/01. https://doi.org/10.1109/IPDPS.2001.925132
Rakhmatov D, Vrudhula S. Minimizing routing configuration cost in dynamically reconfigurable FPGAs. In Proceedings - 15th International Parallel and Distributed Processing Symposium, IPDPS 2001. Institute of Electrical and Electronics Engineers Inc. 2001. p. 1481-1488. 925132 https://doi.org/10.1109/IPDPS.2001.925132
Rakhmatov, D. ; Vrudhula, Sarma. / Minimizing routing configuration cost in dynamically reconfigurable FPGAs. Proceedings - 15th International Parallel and Distributed Processing Symposium, IPDPS 2001. Institute of Electrical and Electronics Engineers Inc., 2001. pp. 1481-1488
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