TY - GEN
T1 - Minimizing routing configuration cost in dynamically reconfigurable FPGAs
AU - Rakhmatov, D.
AU - Vrudhula, S. B.K.
N1 - Funding Information:
This work was carried out at the National Science Foundation's State/Industry/University Cooperative Research Centers' (NSF-S/IUCRC) Center for Low Power Electronics (CLPE). CLPE is supported by the NSF (Grant EEC-9523338), the State of Arizona, and the following companies and foundations: Conexant, Gain Technology, Intel Corporation, Medtronic Microelectronics Center, Microchip Technology, Motorola, Inc., The Motorola Foundation, ON Semiconductor, Philips Semiconductors, Raytheon, Syncron Technologies, LLT, Texas Instruments and Western Design Center.
Publisher Copyright:
© 2001 IEEE.
PY - 2001
Y1 - 2001
N2 - Dynamically reconfigurable computing systems built on FPGAs offer a variety of benefits; however, the reconfiguration cost in terms of power dissipation and delay in such systems is the key negative factor limiting system performance. We describe a hardware organization that allows for simple dynamic placement and routing through introduction of a virtual standard cell topology over an FPGA. We focus on the channel routing issues under the assumption that the FPGA hardware is partially (selectively) reconfigurable. Even though the channel capacity is fixed, routes that cannot fit in the channel at once can share the reconfigurable channel over time. The cost of configuring a new routing pattern can be greatly reduced if portions of the last configured routing pattern are reused. We address the problem of minimization of the configuration cost through maximization of the reuse of an already existing configuration of the channel.
AB - Dynamically reconfigurable computing systems built on FPGAs offer a variety of benefits; however, the reconfiguration cost in terms of power dissipation and delay in such systems is the key negative factor limiting system performance. We describe a hardware organization that allows for simple dynamic placement and routing through introduction of a virtual standard cell topology over an FPGA. We focus on the channel routing issues under the assumption that the FPGA hardware is partially (selectively) reconfigurable. Even though the channel capacity is fixed, routes that cannot fit in the channel at once can share the reconfigurable channel over time. The cost of configuring a new routing pattern can be greatly reduced if portions of the last configured routing pattern are reused. We address the problem of minimization of the configuration cost through maximization of the reuse of an already existing configuration of the channel.
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U2 - 10.1109/IPDPS.2001.925132
DO - 10.1109/IPDPS.2001.925132
M3 - Conference contribution
AN - SCOPUS:27944462361
T3 - Proceedings - 15th International Parallel and Distributed Processing Symposium, IPDPS 2001
SP - 1481
EP - 1488
BT - Proceedings - 15th International Parallel and Distributed Processing Symposium, IPDPS 2001
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 15th International Parallel and Distributed Processing Symposium, IPDPS 2001
Y2 - 23 April 2001 through 27 April 2001
ER -