Methods for designing low-leakage power supply clamps

Timothy J. Maloney, Steven S. Poon, Lawrence T. Clark

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

Low power semiconductor components require minimizing leakage currents including those from ESD protection circuits. Here, MOSFET ESD power clamps with substantial leakage reduction over previous approaches are presented. Designs are described for core logic circuits and for I/O applications where supply voltages exceed what single gate oxides can reliably sustain.

Original languageEnglish (US)
Title of host publicationElectrical Overstress/Electrostatic Discharge Symposium Proceedings
PublisherESD Association
Volume2003-January
ISBN (Print)1585370576, 9781585370573
StatePublished - 2003
Externally publishedYes
Event25th Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2003 - Las Vegas, United States
Duration: Sep 21 2003Sep 25 2003

Other

Other25th Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2003
CountryUnited States
CityLas Vegas
Period9/21/039/25/03

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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