Methodology to optimize critical node separation in hardened flip-flops

Sandeep Shambhulingaiah, Srivatsan Chellappa, Sushil Kumar, Lawrence T. Clark

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

Radiation hardening is a requirement for microelectronic circuits used in aerospace applications as they are prone to radiation induced upsets from high altitude neutrons and ions. The most common method to harden VLSI circuits is to use hardened flip-flops (FFs). The design of these FFs is made more difficult with increasing multi-node charge collection (MNCC) in advanced scaled fabrication processes, which requires that charge storage and other sensitive nodes be separated so that one impinging radiation particle does not affect redundant nodes simultaneously. In this paper we describe a correct by construction design methodology to determine a-priori which hardened FF nodes must be separated, as well as a general interleaving scheme to achieve this separation. We apply the methodology to radiation hardened flip-flops and demonstrate optimal circuit physical organization for protection against multi-node charge collection.

Original languageEnglish (US)
Title of host publicationProceedings - International Symposium on Quality Electronic Design, ISQED
PublisherIEEE Computer Society
Pages486-493
Number of pages8
ISBN (Print)9781479939466
DOIs
StatePublished - 2014
Event15th International Symposium on Quality Electronic Design, ISQED 2014 - Santa Clara, CA, United States
Duration: Mar 3 2014Mar 5 2014

Other

Other15th International Symposium on Quality Electronic Design, ISQED 2014
CountryUnited States
CitySanta Clara, CA
Period3/3/143/5/14

Fingerprint

Flip flop circuits
Radiation
Radiation hardening
Aerospace applications
Networks (circuits)
VLSI circuits
Microelectronics
Neutrons
Fabrication
Ions

Keywords

  • Flip-flop (FF)
  • Multi-Bit Upset (MBU)
  • Radiation Hardening by Design (RHBD)
  • Single Event Effects (SEE)

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

Cite this

Shambhulingaiah, S., Chellappa, S., Kumar, S., & Clark, L. T. (2014). Methodology to optimize critical node separation in hardened flip-flops. In Proceedings - International Symposium on Quality Electronic Design, ISQED (pp. 486-493). [6783364] IEEE Computer Society. https://doi.org/10.1109/ISQED.2014.6783364

Methodology to optimize critical node separation in hardened flip-flops. / Shambhulingaiah, Sandeep; Chellappa, Srivatsan; Kumar, Sushil; Clark, Lawrence T.

Proceedings - International Symposium on Quality Electronic Design, ISQED. IEEE Computer Society, 2014. p. 486-493 6783364.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Shambhulingaiah, S, Chellappa, S, Kumar, S & Clark, LT 2014, Methodology to optimize critical node separation in hardened flip-flops. in Proceedings - International Symposium on Quality Electronic Design, ISQED., 6783364, IEEE Computer Society, pp. 486-493, 15th International Symposium on Quality Electronic Design, ISQED 2014, Santa Clara, CA, United States, 3/3/14. https://doi.org/10.1109/ISQED.2014.6783364
Shambhulingaiah S, Chellappa S, Kumar S, Clark LT. Methodology to optimize critical node separation in hardened flip-flops. In Proceedings - International Symposium on Quality Electronic Design, ISQED. IEEE Computer Society. 2014. p. 486-493. 6783364 https://doi.org/10.1109/ISQED.2014.6783364
Shambhulingaiah, Sandeep ; Chellappa, Srivatsan ; Kumar, Sushil ; Clark, Lawrence T. / Methodology to optimize critical node separation in hardened flip-flops. Proceedings - International Symposium on Quality Electronic Design, ISQED. IEEE Computer Society, 2014. pp. 486-493
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