TY - GEN
T1 - Methodology to optimize critical node separation in hardened flip-flops
AU - Shambhulingaiah, Sandeep
AU - Chellappa, Srivatsan
AU - Kumar, Sushil
AU - Clark, Lawrence T.
PY - 2014/1/1
Y1 - 2014/1/1
N2 - Radiation hardening is a requirement for microelectronic circuits used in aerospace applications as they are prone to radiation induced upsets from high altitude neutrons and ions. The most common method to harden VLSI circuits is to use hardened flip-flops (FFs). The design of these FFs is made more difficult with increasing multi-node charge collection (MNCC) in advanced scaled fabrication processes, which requires that charge storage and other sensitive nodes be separated so that one impinging radiation particle does not affect redundant nodes simultaneously. In this paper we describe a correct by construction design methodology to determine a-priori which hardened FF nodes must be separated, as well as a general interleaving scheme to achieve this separation. We apply the methodology to radiation hardened flip-flops and demonstrate optimal circuit physical organization for protection against multi-node charge collection.
AB - Radiation hardening is a requirement for microelectronic circuits used in aerospace applications as they are prone to radiation induced upsets from high altitude neutrons and ions. The most common method to harden VLSI circuits is to use hardened flip-flops (FFs). The design of these FFs is made more difficult with increasing multi-node charge collection (MNCC) in advanced scaled fabrication processes, which requires that charge storage and other sensitive nodes be separated so that one impinging radiation particle does not affect redundant nodes simultaneously. In this paper we describe a correct by construction design methodology to determine a-priori which hardened FF nodes must be separated, as well as a general interleaving scheme to achieve this separation. We apply the methodology to radiation hardened flip-flops and demonstrate optimal circuit physical organization for protection against multi-node charge collection.
KW - Flip-flop (FF)
KW - Multi-Bit Upset (MBU)
KW - Radiation Hardening by Design (RHBD)
KW - Single Event Effects (SEE)
UR - http://www.scopus.com/inward/record.url?scp=84899488899&partnerID=8YFLogxK
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U2 - 10.1109/ISQED.2014.6783364
DO - 10.1109/ISQED.2014.6783364
M3 - Conference contribution
AN - SCOPUS:84899488899
SN - 9781479939466
T3 - Proceedings - International Symposium on Quality Electronic Design, ISQED
SP - 486
EP - 493
BT - Proceedings of the 15th International Symposium on Quality Electronic Design, ISQED 2014
PB - IEEE Computer Society
T2 - 15th International Symposium on Quality Electronic Design, ISQED 2014
Y2 - 3 March 2014 through 5 March 2014
ER -