Methodology to optimize critical node separation in hardened flip-flops

Sandeep Shambhulingaiah, Srivatsan Chellappa, Sushil Kumar, Lawrence T. Clark

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Scopus citations

Abstract

Radiation hardening is a requirement for microelectronic circuits used in aerospace applications as they are prone to radiation induced upsets from high altitude neutrons and ions. The most common method to harden VLSI circuits is to use hardened flip-flops (FFs). The design of these FFs is made more difficult with increasing multi-node charge collection (MNCC) in advanced scaled fabrication processes, which requires that charge storage and other sensitive nodes be separated so that one impinging radiation particle does not affect redundant nodes simultaneously. In this paper we describe a correct by construction design methodology to determine a-priori which hardened FF nodes must be separated, as well as a general interleaving scheme to achieve this separation. We apply the methodology to radiation hardened flip-flops and demonstrate optimal circuit physical organization for protection against multi-node charge collection.

Original languageEnglish (US)
Title of host publicationProceedings of the 15th International Symposium on Quality Electronic Design, ISQED 2014
PublisherIEEE Computer Society
Pages486-493
Number of pages8
ISBN (Print)9781479939466
DOIs
StatePublished - Jan 1 2014
Event15th International Symposium on Quality Electronic Design, ISQED 2014 - Santa Clara, CA, United States
Duration: Mar 3 2014Mar 5 2014

Publication series

NameProceedings - International Symposium on Quality Electronic Design, ISQED
ISSN (Print)1948-3287
ISSN (Electronic)1948-3295

Other

Other15th International Symposium on Quality Electronic Design, ISQED 2014
CountryUnited States
CitySanta Clara, CA
Period3/3/143/5/14

Keywords

  • Flip-flop (FF)
  • Multi-Bit Upset (MBU)
  • Radiation Hardening by Design (RHBD)
  • Single Event Effects (SEE)

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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  • Cite this

    Shambhulingaiah, S., Chellappa, S., Kumar, S., & Clark, L. T. (2014). Methodology to optimize critical node separation in hardened flip-flops. In Proceedings of the 15th International Symposium on Quality Electronic Design, ISQED 2014 (pp. 486-493). [6783364] (Proceedings - International Symposium on Quality Electronic Design, ISQED). IEEE Computer Society. https://doi.org/10.1109/ISQED.2014.6783364