Methodical design approaches to radiation effects analysis and mitigation in flip-flop circuits

Lawrence T. Clark; Sandeep Shambhulingaiah

doi:10.1109/ISVLSI.2014.74

Methodical design approaches to radiation effects analysis and mitigation in flip-flop circuits

Lawrence T. Clark, Sandeep Shambhulingaiah

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Scopus citations

Abstract

With transistor dimensions shrinking due to continued scaling, integrated circuits are increasingly susceptible to radiation upset. This paper presents a systematic methodology for evaluating circuit hardness, as well as graph clustering approaches to determine effective node separation to protect against upset due to multiple node charge collection. The methodology is circuit simulation based, making it efficient and usable by circuit designers. Example designs are presented to demonstrate the analysis and clustering for real flip-flop designs. Finally, the methodology is utilized to provide critical node separation for a new hardened flip-flop design that reduces the power and area by 27% and 19.5% respectively.

Original language	English (US)
Title of host publication	Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
Publisher	IEEE Computer Society
Pages	595-600
Number of pages	6
ISBN (Electronic)	9781479937639
DOIs	https://doi.org/10.1109/ISVLSI.2014.74
State	Published - Sep 18 2014
Event	2014 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014 - Tampa, United States Duration: Jul 9 2014 → Jul 11 2014

Other

Other	2014 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014
Country/Territory	United States
City	Tampa
Period	7/9/14 → 7/11/14

Keywords

Flip-flop (FF)
Multiple node charge collection (MNCC)
Radiation hardening by design (RHBD)
Single event transient (SET)
Single event upset (SEU)

ASJC Scopus subject areas

Hardware and Architecture
Control and Systems Engineering
Electrical and Electronic Engineering

Access to Document

10.1109/ISVLSI.2014.74

Cite this

Clark, LT & Shambhulingaiah, S 2014, Methodical design approaches to radiation effects analysis and mitigation in flip-flop circuits. in Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI., 6903429, IEEE Computer Society, pp. 595-600, 2014 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014, Tampa, United States, 7/9/14. https://doi.org/10.1109/ISVLSI.2014.74

@inproceedings{4e507083506e46688d820ebb2c7e99d0,

title = "Methodical design approaches to radiation effects analysis and mitigation in flip-flop circuits",

abstract = "With transistor dimensions shrinking due to continued scaling, integrated circuits are increasingly susceptible to radiation upset. This paper presents a systematic methodology for evaluating circuit hardness, as well as graph clustering approaches to determine effective node separation to protect against upset due to multiple node charge collection. The methodology is circuit simulation based, making it efficient and usable by circuit designers. Example designs are presented to demonstrate the analysis and clustering for real flip-flop designs. Finally, the methodology is utilized to provide critical node separation for a new hardened flip-flop design that reduces the power and area by 27% and 19.5% respectively.",

keywords = "Flip-flop (FF), Multiple node charge collection (MNCC), Radiation hardening by design (RHBD), Single event transient (SET), Single event upset (SEU)",

author = "Clark, {Lawrence T.} and Sandeep Shambhulingaiah",

year = "2014",

month = sep,

day = "18",

doi = "10.1109/ISVLSI.2014.74",

language = "English (US)",

pages = "595--600",

booktitle = "Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI",

publisher = "IEEE Computer Society",

note = "2014 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014 ; Conference date: 09-07-2014 Through 11-07-2014",

}

TY - GEN

T1 - Methodical design approaches to radiation effects analysis and mitigation in flip-flop circuits

AU - Clark, Lawrence T.

AU - Shambhulingaiah, Sandeep

PY - 2014/9/18

Y1 - 2014/9/18

N2 - With transistor dimensions shrinking due to continued scaling, integrated circuits are increasingly susceptible to radiation upset. This paper presents a systematic methodology for evaluating circuit hardness, as well as graph clustering approaches to determine effective node separation to protect against upset due to multiple node charge collection. The methodology is circuit simulation based, making it efficient and usable by circuit designers. Example designs are presented to demonstrate the analysis and clustering for real flip-flop designs. Finally, the methodology is utilized to provide critical node separation for a new hardened flip-flop design that reduces the power and area by 27% and 19.5% respectively.

AB - With transistor dimensions shrinking due to continued scaling, integrated circuits are increasingly susceptible to radiation upset. This paper presents a systematic methodology for evaluating circuit hardness, as well as graph clustering approaches to determine effective node separation to protect against upset due to multiple node charge collection. The methodology is circuit simulation based, making it efficient and usable by circuit designers. Example designs are presented to demonstrate the analysis and clustering for real flip-flop designs. Finally, the methodology is utilized to provide critical node separation for a new hardened flip-flop design that reduces the power and area by 27% and 19.5% respectively.

KW - Flip-flop (FF)

KW - Multiple node charge collection (MNCC)

KW - Radiation hardening by design (RHBD)

KW - Single event transient (SET)

KW - Single event upset (SEU)

UR - http://www.scopus.com/inward/record.url?scp=84908212776&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84908212776&partnerID=8YFLogxK

U2 - 10.1109/ISVLSI.2014.74

DO - 10.1109/ISVLSI.2014.74

M3 - Conference contribution

AN - SCOPUS:84908212776

SP - 595

EP - 600

BT - Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI

PB - IEEE Computer Society

T2 - 2014 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014

Y2 - 9 July 2014 through 11 July 2014

ER -

Methodical design approaches to radiation effects analysis and mitigation in flip-flop circuits

Abstract

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Keywords

ASJC Scopus subject areas

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