Memory exploration for low power, embedded systems

Wen Tsong Shiue, Chaitali Chakrabarti

Research output: Chapter in Book/Report/Conference proceedingChapter

116 Scopus citations

Abstract

In embedded system design, the designer has to choose an on-chip memory configuration that is suitable for a specific application. To aid in this design choice, we present a memory exploration strategy based on three performance metrics, namely, cache size, the number of processor cycles and the energy consumption. We show how the performance is affected by cache parameters such as cache size, line size, set associativity and tiling, and the off-chip data organization. We show the importance of including energy in the performance metrics, since an increase in the cache line size, cache size, tiling and set associativity reduces the number of cycles but does not necessarily reduce the energy consumption. These performance metrics help us find the minimum energy cache configuration if time is the hard constraint, or the minimum time cache configuration if energy is the hard constraint.

Original languageEnglish (US)
Title of host publicationProceedings - Design Automation Conference
PublisherIEEE
Pages140-145
Number of pages6
StatePublished - 1999
EventProceedings of the 1999 36th Annual Design Automation Conference (DAC) - New Orleans, LA, USA
Duration: Jun 21 1999Jun 25 1999

Other

OtherProceedings of the 1999 36th Annual Design Automation Conference (DAC)
CityNew Orleans, LA, USA
Period6/21/996/25/99

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering

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    Shiue, W. T., & Chakrabarti, C. (1999). Memory exploration for low power, embedded systems. In Proceedings - Design Automation Conference (pp. 140-145). IEEE.