Abstract
In embedded system design, the designer has to choose an on-chip memory configuration that is suitable for a specific application. To aid in this design choice, we present a memory exploration strategy based on three performance metrics, namely, cache size, the number of processor cycles and the energy consumption. We show how the performance is affected by cache parameters such as cache size, line size, set associativity and tiling, and the off-chip data organization. We show the importance of including energy in the performance metrics, since an increase in the cache line size, cache size, tiling and set associativity reduces the number of cycles but does not necessarily reduce the energy consumption. These performance metrics help us find the minimum energy cache configuration if time is the hard constraint, or the minimum time cache configuration if energy is the hard constraint.
Original language | English (US) |
---|---|
Title of host publication | Proceedings - Design Automation Conference |
Publisher | IEEE |
Pages | 140-145 |
Number of pages | 6 |
State | Published - 1999 |
Event | Proceedings of the 1999 36th Annual Design Automation Conference (DAC) - New Orleans, LA, USA Duration: Jun 21 1999 → Jun 25 1999 |
Other
Other | Proceedings of the 1999 36th Annual Design Automation Conference (DAC) |
---|---|
City | New Orleans, LA, USA |
Period | 6/21/99 → 6/25/99 |
ASJC Scopus subject areas
- Hardware and Architecture
- Control and Systems Engineering