TY - GEN
T1 - Memory exploration for low power embedded systems
AU - Shiue, Wen Tsong
AU - Chakrabarti, Chaitali
N1 - Copyright:
Copyright 2004 Elsevier Science B.V., Amsterdam. All rights reserved.
PY - 1999
Y1 - 1999
N2 - In embedded system design, the designer has to choose an on-chip memory configuration that is suitable for a specific application. To aid in this design choice, we present a memory exploration strategy based on three performance metrics, namely, cache size, the number of processor cycles and the energy consumption. We show how the performance is affected by cache parameters such as cache size, line size, set associativity and tiling, and the off-chip data organization. We show the importance of including energy in the performance metrics, since an increase in the cache line size, cache size, tiling and set associativity reduces the number of cycles but does not necessarily reduce the energy consumption.
AB - In embedded system design, the designer has to choose an on-chip memory configuration that is suitable for a specific application. To aid in this design choice, we present a memory exploration strategy based on three performance metrics, namely, cache size, the number of processor cycles and the energy consumption. We show how the performance is affected by cache parameters such as cache size, line size, set associativity and tiling, and the off-chip data organization. We show the importance of including energy in the performance metrics, since an increase in the cache line size, cache size, tiling and set associativity reduces the number of cycles but does not necessarily reduce the energy consumption.
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M3 - Conference contribution
AN - SCOPUS:0032645780
SN - 0780354729
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - I-250 - I-253
BT - Proceedings - IEEE International Symposium on Circuits and Systems
PB - IEEE
T2 - Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99
Y2 - 30 May 1999 through 2 June 1999
ER -