11 Scopus citations

Abstract

This paper presents novel algorithm-specific techniques to mitigate the effects of failures in SRAM memory caused by voltage scaling and random dopant fluctuations in scaled technologies. We focus on JPEG2000 as a case study. We propose three techniques that exploit the fact that the high frequency subband outputs of the discrete wavelet transform (DWT) have small dynamic range and so errors in the most significant bits can be identified and corrected easily. These schemes do not require any additional memory and have low circuit overhead. We also study several error control coding schemes that are effective in combating errors when the memory failure rates are low. We compare the PSNR versus compression rate performance of the proposed schemes for different memory failure rates. Simulation results show that for high bit error rates (10 -2), the error control coding techniques are not effective and that the algorithm-specific techniques can improve the PSNR quality of up to 10dB higher compared to that of the no-correction case.

Original languageEnglish (US)
Title of host publication2010 IEEE Workshop on Signal Processing Systems, SiPS 2010 - Proceedings
Pages36-41
Number of pages6
DOIs
StatePublished - Dec 27 2010
Event2010 IEEE Workshop on Signal Processing Systems, SiPS 2010 - San Francisco, CA, United States
Duration: Oct 6 2010Oct 8 2010

Publication series

NameIEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
ISSN (Print)1520-6130

Other

Other2010 IEEE Workshop on Signal Processing Systems, SiPS 2010
CountryUnited States
CitySan Francisco, CA
Period10/6/1010/8/10

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Keywords

  • Error tolerance
  • JPEG2000
  • SRAM
  • Voltage scaling

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Signal Processing
  • Applied Mathematics
  • Hardware and Architecture

Cite this

Emre, Y., & Chakrabarti, C. (2010). Memory error compensation techniques for JPEG2000. In 2010 IEEE Workshop on Signal Processing Systems, SiPS 2010 - Proceedings (pp. 36-41). [5624759] (IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation). https://doi.org/10.1109/SIPS.2010.5624759