Memory Design and Exploration for Low Power, Embedded Systems

Wen Tsong Shiue, Chaitali Chakrabarti

Research output: Contribution to journalArticle

20 Scopus citations

Abstract

In this paper, we describe a procedure for memory design and exploration for low power embedded systems. Our system consists of an instruction cache and a data cache on-chip, and a large memory off-chip. In the first step, we try to reduce the power consumption due to memory traffic by applying memory-optimizing transformations such as loop transformations. Next we use a memory exploration procedure to choose a cache configuration (cache size and line size) that satisfies the system requirements of area, number of cycles and energy consumption. We include energy in the performance metrics, since for different cache configurations, the variation in energy consumption is quite different from the variation in the number of cycles. The memory exploration procedure is very efficient since it exploits the trends in the cycles and energy characteristics to reduce the search space significantly.

Original languageEnglish (US)
Pages (from-to)167-178
Number of pages12
JournalJournal of VLSI Signal Processing Systems for Signal, Image, and Video Technology
Volume29
Issue number3
DOIs
StatePublished - Dec 1 2001

Keywords

  • Data cache and instruction cache
  • Loop transformation
  • Memory exploration
  • Memory synthesis

ASJC Scopus subject areas

  • Signal Processing
  • Information Systems
  • Electrical and Electronic Engineering

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