TY - JOUR
T1 - Memory Design and Exploration for Low Power, Embedded Systems
AU - Shiue, Wen Tsong
AU - Chakrabarti, Chaitali
N1 - Funding Information:
The authors would like to thank Shashikiran Tadas of ASU for help with the SimpleScalar experiments. This work was carried out at the National Science Foundation’s State/Industry/University Cooperative Research Center for Low Power Electronics (CLPE). CLPE is supported by the NSF, the State of Arizona and the following companies: Burr Brown, Conexant, Gain Technology, Intel Corporation, Medtronic, Microchip, Motorola, Raytheon, Texas Instruments and Western Design Center.
PY - 2001
Y1 - 2001
N2 - In this paper, we describe a procedure for memory design and exploration for low power embedded systems. Our system consists of an instruction cache and a data cache on-chip, and a large memory off-chip. In the first step, we try to reduce the power consumption due to memory traffic by applying memory-optimizing transformations such as loop transformations. Next we use a memory exploration procedure to choose a cache configuration (cache size and line size) that satisfies the system requirements of area, number of cycles and energy consumption. We include energy in the performance metrics, since for different cache configurations, the variation in energy consumption is quite different from the variation in the number of cycles. The memory exploration procedure is very efficient since it exploits the trends in the cycles and energy characteristics to reduce the search space significantly.
AB - In this paper, we describe a procedure for memory design and exploration for low power embedded systems. Our system consists of an instruction cache and a data cache on-chip, and a large memory off-chip. In the first step, we try to reduce the power consumption due to memory traffic by applying memory-optimizing transformations such as loop transformations. Next we use a memory exploration procedure to choose a cache configuration (cache size and line size) that satisfies the system requirements of area, number of cycles and energy consumption. We include energy in the performance metrics, since for different cache configurations, the variation in energy consumption is quite different from the variation in the number of cycles. The memory exploration procedure is very efficient since it exploits the trends in the cycles and energy characteristics to reduce the search space significantly.
KW - Data cache and instruction cache
KW - Loop transformation
KW - Memory exploration
KW - Memory synthesis
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U2 - 10.1023/A:1012227328646
DO - 10.1023/A:1012227328646
M3 - Article
AN - SCOPUS:0012189992
SN - 1939-8018
VL - 29
SP - 167
EP - 178
JO - Journal of Signal Processing Systems
JF - Journal of Signal Processing Systems
IS - 3
ER -