In this paper, we describe a procedure for memory design and exploration for low power embedded systems. Our procedure tries to reduce the power consumption due to memory traffic by (i) applying memory optimizing transformations such as loop transformations, (ii) storing frequently accessed variables in a register file and an on-chip cache, and (iii) reducing the conflict misses by appropriate choice of cache size and data placement in off chip memory. We then choose a cache configuration (cache size, line size) that satisfies the system requirements of area, number of cycles and energy. We include energy in the performance metrics, since for different cache configurations, the variation in energy is quite different from the variation in the number of cycles. Our memory exploration procedure considers only a selected set of candidate points, thereby reducing the search time significantly.
|Original language||English (US)|
|Number of pages||10|
|Journal||IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation|
|State||Published - Dec 1 1999|
|Event||1999 IEEE Workshop on SiGNAL Processing Systems (SiPS 99): 'Design and Implementation' - Taipei, Taiwan|
Duration: Oct 20 1999 → Oct 22 1999
ASJC Scopus subject areas