Memory access optimization in compilation for coarse-grained reconfigurable architectures

Yongjoo Kim, Jongeun Lee, Aviral Shrivastava, Yunheung Paek

Research output: Contribution to journalArticlepeer-review

18 Scopus citations


Coarse-grained reconfigurable architectures (CGRAs) promise high performance at high power efficiency. They fulfil this promise by keeping the hardware extremely simple, andmoving the complexity to application mapping. One major challenge comes in the form of data mapping. For reasons of power-efficiency and complexity, CGRAs use multibank local memory, and a row of PEs share memory access. In order for each row of the PEs to access any memory bank, there is a hardware arbiter between the memory requests generated by the PEs and the banks of the local memory. However, a fundamental restriction remains in that a bank cannot be accessed by two different PEs at the same time. We propose to meet this challenge by mapping application operations onto PEs and data into memory banks in a way that avoids such conflicts. To further improve performance on multibank memories, we propose a compiler optimization for CGRA mapping to reduce the number of memory operations by exploiting data reuse. Our experimental results on kernels from multimedia benchmarks demonstrate that our local memory-aware compilation approach can generate mappings that are up to 53% better in performance (26% on average) compared to a memoryunaware scheduler.

Original languageEnglish (US)
Article number42
JournalACM Transactions on Design Automation of Electronic Systems
Issue number4
StatePublished - Oct 1 2011


  • Array mapping
  • Bank conflict
  • Coarse-grained reconfigurable architecture
  • Compilation
  • Multibank memory

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering


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