TY - JOUR
T1 - MeF-RAM
T2 - A New Non-Volatile Cache Memory Based on Magneto-Electric FET
AU - Angizi, Shaahin
AU - Khoshavi, Navid
AU - Marshall, Andrew
AU - Dowben, Peter
AU - Fan, Deliang
N1 - Funding Information:
This work is supported in part by the National Science Foundation under Grants No. 2005209 and No. 2003749, and EPSCoR RII Track-1: Emergent Quantum Materials and Technologies (EQUATE), Award OIA-2044049. Authors’ addresses: S. Angizi and D. Fan, School of Electrical, Computer and Energy Engineering, Arizona State University, 650 E Tyler Mall, Tempe, Arizona 85287-5706; emails: {sangizi, dfan}@asu.edu; N. Khoshavi, AMD, Orlando, Florida 32817; email: navid.khoshavi@amd.com; A. Marshall, Electrical and Computer Engineering Department, University of Texas at Dallas, Richardson, Texas 75080-3021; email: andrew.marshall@utdallas.edu; P. Dowben, Department of Physics and Astronomy, University of Nebraska-Lincoln, Lincoln, Nebraska 68588-0299; email: pdowben@unl.edu. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from permissions@acm.org. © 2021 Association for Computing Machinery. 1084-4309/2021/11-ART18 $15.00 https://doi.org/10.1145/3484222
Publisher Copyright:
© 2021 Association for Computing Machinery.
PY - 2022/3
Y1 - 2022/3
N2 - Magneto-Electric FET (MEFET) is a recently developed post-CMOS FET, which offers intriguing characteristics for high-speed and low-power design in both logic and memory applications. In this article, we present MeF-RAM, a non-volatile cache memory design based on 2-Transistor-1-MEFET (2T1M) memory bit-cell with separate read and write paths. We show that with proper co-design across MEFET device, memory cell circuit, and array architecture, MeF-RAM is a promising candidate for fast non-volatile memory (NVM). To evaluate its cache performance in the memory system, we, for the first time, build a device-to-architecture cross-layer evaluation framework to quantitatively analyze and benchmark the MeF-RAM design with other memory technologies, including both volatile memory (i.e., SRAM, eDRAM) and other popular non-volatile emerging memory (i.e., ReRAM, STT-MRAM, and SOT-MRAM). The experiment results for the PARSEC benchmark suite indicate that, as an L2 cache memory, MeF-RAM reduces Energy Area Latency (EAT) product on average by ∼98% and ∼70% compared with typical 6T-SRAM and 2T1R SOT-MRAM counterparts, respectively.
AB - Magneto-Electric FET (MEFET) is a recently developed post-CMOS FET, which offers intriguing characteristics for high-speed and low-power design in both logic and memory applications. In this article, we present MeF-RAM, a non-volatile cache memory design based on 2-Transistor-1-MEFET (2T1M) memory bit-cell with separate read and write paths. We show that with proper co-design across MEFET device, memory cell circuit, and array architecture, MeF-RAM is a promising candidate for fast non-volatile memory (NVM). To evaluate its cache performance in the memory system, we, for the first time, build a device-to-architecture cross-layer evaluation framework to quantitatively analyze and benchmark the MeF-RAM design with other memory technologies, including both volatile memory (i.e., SRAM, eDRAM) and other popular non-volatile emerging memory (i.e., ReRAM, STT-MRAM, and SOT-MRAM). The experiment results for the PARSEC benchmark suite indicate that, as an L2 cache memory, MeF-RAM reduces Energy Area Latency (EAT) product on average by ∼98% and ∼70% compared with typical 6T-SRAM and 2T1R SOT-MRAM counterparts, respectively.
KW - Magneto-electric FETs
KW - cache design
KW - memory bit-cell
KW - non-volatile memory
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U2 - 10.1145/3484222
DO - 10.1145/3484222
M3 - Article
AN - SCOPUS:85125320649
SN - 1084-4309
VL - 27
JO - ACM Transactions on Design Automation of Electronic Systems
JF - ACM Transactions on Design Automation of Electronic Systems
IS - 2
M1 - 18
ER -