MeF-RAM: A New Non-Volatile Cache Memory Based on Magneto-Electric FET

Shaahin Angizi, Navid Khoshavi, Andrew Marshall, Peter Dowben, Deliang Fan

Research output: Contribution to journalArticlepeer-review

Abstract

Magneto-Electric FET (MEFET) is a recently developed post-CMOS FET, which offers intriguing characteristics for high-speed and low-power design in both logic and memory applications. In this article, we present MeF-RAM, a non-volatile cache memory design based on 2-Transistor-1-MEFET (2T1M) memory bit-cell with separate read and write paths. We show that with proper co-design across MEFET device, memory cell circuit, and array architecture, MeF-RAM is a promising candidate for fast non-volatile memory (NVM). To evaluate its cache performance in the memory system, we, for the first time, build a device-to-architecture cross-layer evaluation framework to quantitatively analyze and benchmark the MeF-RAM design with other memory technologies, including both volatile memory (i.e., SRAM, eDRAM) and other popular non-volatile emerging memory (i.e., ReRAM, STT-MRAM, and SOT-MRAM). The experiment results for the PARSEC benchmark suite indicate that, as an L2 cache memory, MeF-RAM reduces Energy Area Latency (EAT) product on average by ∼98% and ∼70% compared with typical 6T-SRAM and 2T1R SOT-MRAM counterparts, respectively.

Original languageEnglish (US)
Article number18
JournalACM Transactions on Design Automation of Electronic Systems
Volume27
Issue number2
DOIs
StatePublished - Mar 2022

Keywords

  • cache design
  • Magneto-electric FETs
  • memory bit-cell
  • non-volatile memory

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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