Median filter architecture based on sorting networks

Chaitali Chakrabarti, Suhel Dhanani

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

This paper presents a sorting network based architecture for computing 2-dimensional median filters in real-time. The median computing network is a modified version of Batcher's sorting network with compare-swap units which sort 2 elements (sort-S) as well as 3 elements (sort-3) in 1 time unit. Introduction of sort-3 units reduces the latency of the network without loss of regularity. A (3 x 3) median filter has been implemented in 2 micron CMOS using this approach. The architecture is completely pipelined and operates in the bit-serial mode with 8 bit precision. The operating speed is 40 MHz.

Original languageEnglish (US)
Title of host publication1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1069-1072
Number of pages4
ISBN (Electronic)0780305930
DOIs
StatePublished - Jan 1 1992
Event1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992 - San Diego, United States
Duration: May 10 1992May 13 1992

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume3
ISSN (Print)0271-4310

Conference

Conference1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
CountryUnited States
CitySan Diego
Period5/10/925/13/92

Fingerprint

Median filters
Sorting

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Chakrabarti, C., & Dhanani, S. (1992). Median filter architecture based on sorting networks. In 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992 (pp. 1069-1072). [230295] (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 3). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.1992.230295

Median filter architecture based on sorting networks. / Chakrabarti, Chaitali; Dhanani, Suhel.

1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992. Institute of Electrical and Electronics Engineers Inc., 1992. p. 1069-1072 230295 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 3).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Chakrabarti, C & Dhanani, S 1992, Median filter architecture based on sorting networks. in 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992., 230295, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 3, Institute of Electrical and Electronics Engineers Inc., pp. 1069-1072, 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992, San Diego, United States, 5/10/92. https://doi.org/10.1109/ISCAS.1992.230295
Chakrabarti C, Dhanani S. Median filter architecture based on sorting networks. In 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992. Institute of Electrical and Electronics Engineers Inc. 1992. p. 1069-1072. 230295. (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.1992.230295
Chakrabarti, Chaitali ; Dhanani, Suhel. / Median filter architecture based on sorting networks. 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992. Institute of Electrical and Electronics Engineers Inc., 1992. pp. 1069-1072 (Proceedings - IEEE International Symposium on Circuits and Systems).
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