TY - GEN
T1 - Median filter architecture based on sorting networks
AU - Chakrabarti, Chaitali
AU - Dhanani, Suhel
N1 - Publisher Copyright:
© 1992 IEEE.
PY - 1992
Y1 - 1992
N2 - This paper presents a sorting network based architecture for computing 2-dimensional median filters in real-time. The median computing network is a modified version of Batcher's sorting network with compare-swap units which sort 2 elements (sort-S) as well as 3 elements (sort-3) in 1 time unit. Introduction of sort-3 units reduces the latency of the network without loss of regularity. A (3 x 3) median filter has been implemented in 2 micron CMOS using this approach. The architecture is completely pipelined and operates in the bit-serial mode with 8 bit precision. The operating speed is 40 MHz.
AB - This paper presents a sorting network based architecture for computing 2-dimensional median filters in real-time. The median computing network is a modified version of Batcher's sorting network with compare-swap units which sort 2 elements (sort-S) as well as 3 elements (sort-3) in 1 time unit. Introduction of sort-3 units reduces the latency of the network without loss of regularity. A (3 x 3) median filter has been implemented in 2 micron CMOS using this approach. The architecture is completely pipelined and operates in the bit-serial mode with 8 bit precision. The operating speed is 40 MHz.
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U2 - 10.1109/ISCAS.1992.230295
DO - 10.1109/ISCAS.1992.230295
M3 - Conference contribution
AN - SCOPUS:85024232636
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 1069
EP - 1072
BT - 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
Y2 - 10 May 1992 through 13 May 1992
ER -