Measurements and Simulation of Self-Heating in 40 nm SOI MOSFETs

Xiong Zhang, Payam Mehr, Dragica Vasileska, Trevor Thornton

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

To understand self-heating in SOI CMOS, conventional and trap-rich substrates are used to fabricate 40nm gate length NFET pairs that share the same active region. One NFET serves as a heater, while the other is used as a calibrated thermometer. Measurements of the local heating confirm the simulated temperature distribution. Heat flow out of the metal contacts reduces the self-heating in NFETs on trap-rich substrates which have reduced thermal conductivity compared to conventional SOI wafers.

Original languageEnglish (US)
Title of host publication2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728181769
DOIs
StatePublished - Apr 8 2021
Event5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021 - Chengdu, China
Duration: Apr 8 2021Apr 11 2021

Publication series

Name2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021

Conference

Conference5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021
Country/TerritoryChina
CityChengdu
Period4/8/214/11/21

Keywords

  • CMOS
  • Self-heating effect (SHE)
  • modeling and simulation
  • silicon-on-insulator (SOI)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Industrial and Manufacturing Engineering
  • Electronic, Optical and Magnetic Materials

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