Mapping statistical process variations toward circuit performance variability: An analytical modeling approach

Yu Cao, Lawrence T. Clark

Research output: Chapter in Book/Report/Conference proceedingConference contribution

81 Scopus citations

Abstract

A physical yet compact gate delay model is developed integrating short-channel effects and the Alpha-power law based timing model. This analytical approach accurately predicts both nominal delay and delay variability over a wide range of bias conditions, including sub-threshold. Excellent model scalability enables efficient mapping between process variations and delay variability at the circuit level. Based on this model, relative importance of physical effects on delay variability has been identified. While effective channel length variation is the leading source for variability at current 90nm node, performance variability is actually more sensitive to threshold variation at the sub-threshold region. Furthermore, this model is applied to investigate the limitation of low power design techniques in the presence of process variations, particularly dual V th and L biasing. Due to excessive variability under low V DD, these techniques become ineffective.

Original languageEnglish (US)
Title of host publicationProceedings - Design Automation Conference
Pages658-663
Number of pages6
Publication statusPublished - 2005
Event42nd Design Automation Conference, DAC 2005 - Anaheim, CA, United States
Duration: Jun 13 2005Jun 17 2005

Other

Other42nd Design Automation Conference, DAC 2005
CountryUnited States
CityAnaheim, CA
Period6/13/056/17/05

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Keywords

  • Delay
  • Process Variations
  • Variability

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering

Cite this

Cao, Y., & Clark, L. T. (2005). Mapping statistical process variations toward circuit performance variability: An analytical modeling approach. In Proceedings - Design Automation Conference (pp. 658-663). [40.2]