Mapping statistical process variations toward circuit performance variability: An analytical modeling approach

Yu Cao, Lawrence T. Clark

Research output: Contribution to journalArticlepeer-review

42 Scopus citations

Abstract

An analytical gate delay model is developed by integrating short-channel effects and the Alpha-power law-based timing model. As verified with an industrial 90-nm technology, this analytical approach accurately predicts both nominal delay and delay variability over a wide range of power supply conditions including subthreshold and strong-inversion regions. Excellent model scalability enables efficient mapping between process variations and delay variability at the gate level. Based on this model, the impact of various physical effects on delay variability has been identified. While the variation of effective channel length is the leading source for delay variability at the current 90-nm node, delay variability is actually more sensitive to the variation of threshold voltage, especially in the subthreshold region. Furthermore, the limitation of low-power design techniques is investigated in the presence of process variations, particularly-dual Vth and L biasing. These techniques become less effective at low VDD due to excessive delay variability.

Original languageEnglish (US)
Pages (from-to)1866-1873
Number of pages8
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume26
Issue number10
DOIs
StatePublished - Oct 1 2007

Keywords

  • Channel length
  • Delay variability
  • Gate delay
  • Process variations
  • Threshold voltage

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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