Managing Standby and Active Mode Leakage Power in Deep Sub-micron Design

Lawrence T. Clark, Rakesh Patel, Timothy S. Beatty

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

Scaling has allowed rising transistor counts per die and increases leakage at an exponential rate, making power a primary constraint in all integrated circuit designs. Future designs must address emerging leakage components due to direct band to band tunneling, through MOSFET oxides and at steep junction doping gradients. In this paper, we describe circuit design techniques for managing leakage power, both during standby and for limiting the leakage power contribution during active operation. The efficacy, design effort, and process ramifications of different approaches are examined. The schemes are primarily aimed at hand-held devices such as cell phones, since the needs for low power are most acute in these markets due to limited battery capacity.

Original languageEnglish (US)
Title of host publicationProceedings of the International Symposium on Low Power Electronics and Design
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages274-279
Number of pages6
Volume2004-January
EditionJanuary
DOIs
StatePublished - 2004
Externally publishedYes
Event2004 International Symposium on Low Power Electronics and Design, ISLPED 2004 - Newport Beach, United States
Duration: Aug 9 2004Aug 11 2004

Other

Other2004 International Symposium on Low Power Electronics and Design, ISLPED 2004
CountryUnited States
CityNewport Beach
Period8/9/048/11/04

Fingerprint

Transistors
Doping (additives)
Oxides
Networks (circuits)
Integrated circuit design

Keywords

  • battery lifetime
  • Drowsy mode
  • MTCMOS
  • SRAM leakage control
  • TGSRAM
  • thick gate shadow latch
  • transistor leakage

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Clark, L. T., Patel, R., & Beatty, T. S. (2004). Managing Standby and Active Mode Leakage Power in Deep Sub-micron Design. In Proceedings of the International Symposium on Low Power Electronics and Design (January ed., Vol. 2004-January, pp. 274-279). [1349350] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/LPE.2004.241060

Managing Standby and Active Mode Leakage Power in Deep Sub-micron Design. / Clark, Lawrence T.; Patel, Rakesh; Beatty, Timothy S.

Proceedings of the International Symposium on Low Power Electronics and Design. Vol. 2004-January January. ed. Institute of Electrical and Electronics Engineers Inc., 2004. p. 274-279 1349350.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Clark, LT, Patel, R & Beatty, TS 2004, Managing Standby and Active Mode Leakage Power in Deep Sub-micron Design. in Proceedings of the International Symposium on Low Power Electronics and Design. January edn, vol. 2004-January, 1349350, Institute of Electrical and Electronics Engineers Inc., pp. 274-279, 2004 International Symposium on Low Power Electronics and Design, ISLPED 2004, Newport Beach, United States, 8/9/04. https://doi.org/10.1109/LPE.2004.241060
Clark LT, Patel R, Beatty TS. Managing Standby and Active Mode Leakage Power in Deep Sub-micron Design. In Proceedings of the International Symposium on Low Power Electronics and Design. January ed. Vol. 2004-January. Institute of Electrical and Electronics Engineers Inc. 2004. p. 274-279. 1349350 https://doi.org/10.1109/LPE.2004.241060
Clark, Lawrence T. ; Patel, Rakesh ; Beatty, Timothy S. / Managing Standby and Active Mode Leakage Power in Deep Sub-micron Design. Proceedings of the International Symposium on Low Power Electronics and Design. Vol. 2004-January January. ed. Institute of Electrical and Electronics Engineers Inc., 2004. pp. 274-279
@inproceedings{99e207de44e64eeeaba29ca5cfb19e35,
title = "Managing Standby and Active Mode Leakage Power in Deep Sub-micron Design",
abstract = "Scaling has allowed rising transistor counts per die and increases leakage at an exponential rate, making power a primary constraint in all integrated circuit designs. Future designs must address emerging leakage components due to direct band to band tunneling, through MOSFET oxides and at steep junction doping gradients. In this paper, we describe circuit design techniques for managing leakage power, both during standby and for limiting the leakage power contribution during active operation. The efficacy, design effort, and process ramifications of different approaches are examined. The schemes are primarily aimed at hand-held devices such as cell phones, since the needs for low power are most acute in these markets due to limited battery capacity.",
keywords = "battery lifetime, Drowsy mode, MTCMOS, SRAM leakage control, TGSRAM, thick gate shadow latch, transistor leakage",
author = "Clark, {Lawrence T.} and Rakesh Patel and Beatty, {Timothy S.}",
year = "2004",
doi = "10.1109/LPE.2004.241060",
language = "English (US)",
volume = "2004-January",
pages = "274--279",
booktitle = "Proceedings of the International Symposium on Low Power Electronics and Design",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
edition = "January",

}

TY - GEN

T1 - Managing Standby and Active Mode Leakage Power in Deep Sub-micron Design

AU - Clark, Lawrence T.

AU - Patel, Rakesh

AU - Beatty, Timothy S.

PY - 2004

Y1 - 2004

N2 - Scaling has allowed rising transistor counts per die and increases leakage at an exponential rate, making power a primary constraint in all integrated circuit designs. Future designs must address emerging leakage components due to direct band to band tunneling, through MOSFET oxides and at steep junction doping gradients. In this paper, we describe circuit design techniques for managing leakage power, both during standby and for limiting the leakage power contribution during active operation. The efficacy, design effort, and process ramifications of different approaches are examined. The schemes are primarily aimed at hand-held devices such as cell phones, since the needs for low power are most acute in these markets due to limited battery capacity.

AB - Scaling has allowed rising transistor counts per die and increases leakage at an exponential rate, making power a primary constraint in all integrated circuit designs. Future designs must address emerging leakage components due to direct band to band tunneling, through MOSFET oxides and at steep junction doping gradients. In this paper, we describe circuit design techniques for managing leakage power, both during standby and for limiting the leakage power contribution during active operation. The efficacy, design effort, and process ramifications of different approaches are examined. The schemes are primarily aimed at hand-held devices such as cell phones, since the needs for low power are most acute in these markets due to limited battery capacity.

KW - battery lifetime

KW - Drowsy mode

KW - MTCMOS

KW - SRAM leakage control

KW - TGSRAM

KW - thick gate shadow latch

KW - transistor leakage

UR - http://www.scopus.com/inward/record.url?scp=84932167700&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84932167700&partnerID=8YFLogxK

U2 - 10.1109/LPE.2004.241060

DO - 10.1109/LPE.2004.241060

M3 - Conference contribution

AN - SCOPUS:84932167700

VL - 2004-January

SP - 274

EP - 279

BT - Proceedings of the International Symposium on Low Power Electronics and Design

PB - Institute of Electrical and Electronics Engineers Inc.

ER -