Managing Standby and Active Mode Leakage Power in Deep Sub-micron Design

Lawrence T. Clark; Rakesh Patel; Timothy S. Beatty

doi:10.1109/LPE.2004.241060

Managing Standby and Active Mode Leakage Power in Deep Sub-micron Design

Lawrence T. Clark, Rakesh Patel, Timothy S. Beatty

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Scopus citations

Abstract

Scaling has allowed rising transistor counts per die and increases leakage at an exponential rate, making power a primary constraint in all integrated circuit designs. Future designs must address emerging leakage components due to direct band to band tunneling, through MOSFET oxides and at steep junction doping gradients. In this paper, we describe circuit design techniques for managing leakage power, both during standby and for limiting the leakage power contribution during active operation. The efficacy, design effort, and process ramifications of different approaches are examined. The schemes are primarily aimed at hand-held devices such as cell phones, since the needs for low power are most acute in these markets due to limited battery capacity.

Original language	English (US)
Title of host publication	Proceedings of the International Symposium on Low Power Electronics and Design
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	274-279
Number of pages	6
Volume	2004-January
Edition	January
DOIs	https://doi.org/10.1109/LPE.2004.241060
State	Published - 2004
Externally published	Yes
Event	2004 International Symposium on Low Power Electronics and Design, ISLPED 2004 - Newport Beach, United States Duration: Aug 9 2004 → Aug 11 2004

Other

Other	2004 International Symposium on Low Power Electronics and Design, ISLPED 2004
Country/Territory	United States
City	Newport Beach
Period	8/9/04 → 8/11/04

Keywords

battery lifetime
Drowsy mode
MTCMOS
SRAM leakage control
TGSRAM
thick gate shadow latch
transistor leakage

ASJC Scopus subject areas

General Engineering

Access to Document

10.1109/LPE.2004.241060

Cite this

Managing Standby and Active Mode Leakage Power in Deep Sub-micron Design. / Clark, Lawrence T.; Patel, Rakesh; Beatty, Timothy S.
Proceedings of the International Symposium on Low Power Electronics and Design. Vol. 2004-January January. ed. Institute of Electrical and Electronics Engineers Inc., 2004. p. 274-279 1349350.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Clark, LT, Patel, R & Beatty, TS 2004, Managing Standby and Active Mode Leakage Power in Deep Sub-micron Design. in Proceedings of the International Symposium on Low Power Electronics and Design. January edn, vol. 2004-January, 1349350, Institute of Electrical and Electronics Engineers Inc., pp. 274-279, 2004 International Symposium on Low Power Electronics and Design, ISLPED 2004, Newport Beach, United States, 8/9/04. https://doi.org/10.1109/LPE.2004.241060

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abstract = "Scaling has allowed rising transistor counts per die and increases leakage at an exponential rate, making power a primary constraint in all integrated circuit designs. Future designs must address emerging leakage components due to direct band to band tunneling, through MOSFET oxides and at steep junction doping gradients. In this paper, we describe circuit design techniques for managing leakage power, both during standby and for limiting the leakage power contribution during active operation. The efficacy, design effort, and process ramifications of different approaches are examined. The schemes are primarily aimed at hand-held devices such as cell phones, since the needs for low power are most acute in these markets due to limited battery capacity.",

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KW - battery lifetime

KW - Drowsy mode

KW - MTCMOS

KW - SRAM leakage control

KW - TGSRAM

KW - thick gate shadow latch

KW - transistor leakage

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Managing Standby and Active Mode Leakage Power in Deep Sub-micron Design

Abstract

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Keywords

ASJC Scopus subject areas

Access to Document

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