Managing standby and active mode leakage power in deep sub-micron design

Lawrence T. Clark, Rakesh Patel, Timothy S. Beatty

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Scopus citations

Abstract

Scaling has allowed rising transistor counts per die and increases leakage at an exponential rate, making power a primary constraint in all integrated circuit designs. Future designs must address emerging leakage components due to direct band to band tunneling, through MOSFET oxides and at steep junction doping gradients. In this paper, we describe circuit design techniques for managing leakage power, both during standby and for limiting the leakage power contribution during active operation. The efficacy, design effort, and process ramifications of different approaches are examined. The schemes are primarily aimed at hand-held devices such as cell phones, since the needs for low power are most acute in these markets due to limited battery capacity.

Original languageEnglish (US)
Title of host publicationProceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04
Pages274-279
Number of pages6
StatePublished - Dec 1 2004
EventProceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04 - Newport Beach, CA, United States
Duration: Aug 9 2004Aug 11 2004

Publication series

NameProceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04

Other

OtherProceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04
CountryUnited States
CityNewport Beach, CA
Period8/9/048/11/04

Keywords

  • Battery lifetime
  • Drowsy mode
  • MTCMOS
  • SRAM leakage control
  • TGSRAM
  • Thick gate shadow latch
  • Transistor leakage

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Clark, L. T., Patel, R., & Beatty, T. S. (2004). Managing standby and active mode leakage power in deep sub-micron design. In Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04 (pp. 274-279). (Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04).