TY - JOUR
T1 - Majority-Based Spin-CMOS Primitives for Approximate Computing
AU - Angizi, Shaahin
AU - Jiang, Honglan
AU - DeMara, Ronald F.
AU - Han, Jie
AU - Fan, Deliang
N1 - Funding Information:
Manuscript received March 29, 2018; accepted May 6, 2018. Date of publication May 15, 2018; date of current version July 9, 2018. This work was partly supported by the Natural Sciences and Engineering Research Council (NSERC) of Canada (Project Number: RES0025211) and the National Science Foundation under Grant No. 1740126 and Semiconductor Research Corporation nCORE. The review of this paper was arranged by Associate Editor W. Zhao. (Corresponding author: Jie Han.) S. Angizi, R. F. DeMara, and D. Fan are with the Department of Electrical and Computer Engineering, University of Central Florida, Orlando, FL 32816 USA (e-mail:,angizi@knights.ucf.edu; ronald.demara@ucf.edu; dfan@ucf.edu).
Publisher Copyright:
© 2018 IEEE.
PY - 2018/7
Y1 - 2018/7
N2 - Promising for digital signal processing applications, approximate computing has been extensively considered to tradeoff limited accuracy for improvements in other circuit metrics such as area, power, and performance. In this paper, approximate arithmetic circuits are proposed by using emerging nanoscale spintronic devices. Leveraging the intrinsic current-mode thresholding operation of spintronic devices, we initially present a hybrid spin-CMOS majority gate design based on a composite spintronic device structure consisting of a magnetic domain wall motion stripe and a magnetic tunnel junction. We further propose a compact and energy-efficient accuracy-configurable adder design based on the majority gate. Unlike most previous approximate circuit designs that hardwire a constant degree of approximation, this design is adaptive to the inherent resilience in various applications to different degrees of accuracy. Subsequently, we propose two new approximate compressors for utilization in fast multiplier designs. The device-circuit SPICE simulation shows 34.58% and 66% improvement in power consumption, respectively, for the accurate and approximate modes of the accuracy-configurable adder, compared to the recently reported domain wall motion-based full adder design. In addition, the proposed accuracy-configurable adder and approximate compressors can be efficiently utilized in the discrete cosine transform (DCT) as a widely-used digital image processing algorithm. The results indicate that the DCT and inverse DCT (IDCT) using the approximate multiplier achieve ∼2x energy saving and 3x speed-up compared to an exactly-designed circuit, while achieving comparable quality in its output result.
AB - Promising for digital signal processing applications, approximate computing has been extensively considered to tradeoff limited accuracy for improvements in other circuit metrics such as area, power, and performance. In this paper, approximate arithmetic circuits are proposed by using emerging nanoscale spintronic devices. Leveraging the intrinsic current-mode thresholding operation of spintronic devices, we initially present a hybrid spin-CMOS majority gate design based on a composite spintronic device structure consisting of a magnetic domain wall motion stripe and a magnetic tunnel junction. We further propose a compact and energy-efficient accuracy-configurable adder design based on the majority gate. Unlike most previous approximate circuit designs that hardwire a constant degree of approximation, this design is adaptive to the inherent resilience in various applications to different degrees of accuracy. Subsequently, we propose two new approximate compressors for utilization in fast multiplier designs. The device-circuit SPICE simulation shows 34.58% and 66% improvement in power consumption, respectively, for the accurate and approximate modes of the accuracy-configurable adder, compared to the recently reported domain wall motion-based full adder design. In addition, the proposed accuracy-configurable adder and approximate compressors can be efficiently utilized in the discrete cosine transform (DCT) as a widely-used digital image processing algorithm. The results indicate that the DCT and inverse DCT (IDCT) using the approximate multiplier achieve ∼2x energy saving and 3x speed-up compared to an exactly-designed circuit, while achieving comparable quality in its output result.
KW - Approximate computing
KW - accuracy-configurable adder
KW - compressor
KW - domain wall motion device
KW - spintronic
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U2 - 10.1109/TNANO.2018.2836918
DO - 10.1109/TNANO.2018.2836918
M3 - Article
AN - SCOPUS:85047010342
SN - 1536-125X
VL - 17
SP - 795
EP - 806
JO - IEEE Transactions on Nanotechnology
JF - IEEE Transactions on Nanotechnology
IS - 4
ER -