MAGELLAN: Multiway hardware-software partitioning and scheduling for latency minimization of hierarchical control-dataflow task graphs

K. S. Chatha, R. Vemuri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

33 Scopus citations

Abstract

The paper presents MAGELLAN, a heuristic technique for mapping hierarchical control-dataflow task graph specifications on heterogeneous architecture templates. The architecture can consist of multiple hardware and software processing elements as specified by the user. The objective of the technique is to minimize the worst case latency of the task graph subject to the area constraints on the architecture. The technique uses an iterative approach consisting of closely linked hardware-software partitioner and scheduler. Both the partitioner and scheduler operate on the task graph in a hierarchical top down manner. The technique optimizes deterministic loop constructs by applying clustering, unrolling and pipelining. The technique considers speculative execution for conditional constructs. The number of actual hardware/software implementations of a function in the task graph are also optimized by the technique. The effectiveness of the technique is demonstrated by a case study of an image compression algori thm.

Original languageEnglish (US)
Title of host publicationHardware/Software Codesign - Proceedings of the International Workshop
Pages42-47
Number of pages6
StatePublished - 2001
Externally publishedYes
Event9th International Symposium on Hardware/Software Codesign - Copenhagen, Denmark
Duration: Apr 25 2001Apr 27 2001

Other

Other9th International Symposium on Hardware/Software Codesign
CountryDenmark
CityCopenhagen
Period4/25/014/27/01

ASJC Scopus subject areas

  • Hardware and Architecture

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