Macro-instruction generation for dynamic logic caching

Kendel McCarley; Sarma B K Vrudhula

Macro-instruction generation for dynamic logic caching

Computing and Augmented Intelligence, School of (IAFSE-SCAI)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper outlines the synthesis of macro-instructions for dynamically reprogrammable FPGAs so that they may be easily generated, placed, and garbage collected at run-time. An overview of a dynamic logic caching computer that uses these macro-instructions is given and their use within this environment discussed. The synthesis of macro-instructions is illustrated with a basic example. Finally, the current state of development of a logic cache based computing platform and compiler/simulator workframe is presented.

Original language	English (US)
Title of host publication	Proceedings of the International Workshop on Rapid System Prototyping
Editors	Anon
Publisher	IEEE
Pages	63-69
Number of pages	7
State	Published - 1997
Event	Proceedings of the 1997 8th IEEE International Workshop on Rapid System Prototyping, RSP - Chapel Hill, NC, USA Duration: Jun 24 1997 → Jun 26 1997

Other

Other	Proceedings of the 1997 8th IEEE International Workshop on Rapid System Prototyping, RSP
City	Chapel Hill, NC, USA
Period	6/24/97 → 6/26/97

ASJC Scopus subject areas

Software
Safety, Risk, Reliability and Quality

Cite this

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title = "Macro-instruction generation for dynamic logic caching",

abstract = "This paper outlines the synthesis of macro-instructions for dynamically reprogrammable FPGAs so that they may be easily generated, placed, and garbage collected at run-time. An overview of a dynamic logic caching computer that uses these macro-instructions is given and their use within this environment discussed. The synthesis of macro-instructions is illustrated with a basic example. Finally, the current state of development of a logic cache based computing platform and compiler/simulator workframe is presented.",

author = "Kendel McCarley and Vrudhula, {Sarma B K}",

year = "1997",

language = "English (US)",

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note = "Proceedings of the 1997 8th IEEE International Workshop on Rapid System Prototyping, RSP ; Conference date: 24-06-1997 Through 26-06-1997",

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AB - This paper outlines the synthesis of macro-instructions for dynamically reprogrammable FPGAs so that they may be easily generated, placed, and garbage collected at run-time. An overview of a dynamic logic caching computer that uses these macro-instructions is given and their use within this environment discussed. The synthesis of macro-instructions is illustrated with a basic example. Finally, the current state of development of a logic cache based computing platform and compiler/simulator workframe is presented.

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M3 - Conference contribution

AN - SCOPUS:0030651556

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BT - Proceedings of the International Workshop on Rapid System Prototyping

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T2 - Proceedings of the 1997 8th IEEE International Workshop on Rapid System Prototyping, RSP

Y2 - 24 June 1997 through 26 June 1997

ER -

Macro-instruction generation for dynamic logic caching

Abstract

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ASJC Scopus subject areas

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