Macro-instruction generation for dynamic logic caching

Kendel McCarley, Sarma B K Vrudhula

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper outlines the synthesis of macro-instructions for dynamically reprogrammable FPGAs so that they may be easily generated, placed, and garbage collected at run-time. An overview of a dynamic logic caching computer that uses these macro-instructions is given and their use within this environment discussed. The synthesis of macro-instructions is illustrated with a basic example. Finally, the current state of development of a logic cache based computing platform and compiler/simulator workframe is presented.

Original languageEnglish (US)
Title of host publicationProceedings of the International Workshop on Rapid System Prototyping
Editors Anon
PublisherIEEE
Pages63-69
Number of pages7
StatePublished - 1997
Externally publishedYes
EventProceedings of the 1997 8th IEEE International Workshop on Rapid System Prototyping, RSP - Chapel Hill, NC, USA
Duration: Jun 24 1997Jun 26 1997

Other

OtherProceedings of the 1997 8th IEEE International Workshop on Rapid System Prototyping, RSP
CityChapel Hill, NC, USA
Period6/24/976/26/97

ASJC Scopus subject areas

  • Software
  • Safety, Risk, Reliability and Quality

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  • Cite this

    McCarley, K., & Vrudhula, S. B. K. (1997). Macro-instruction generation for dynamic logic caching. In Anon (Ed.), Proceedings of the International Workshop on Rapid System Prototyping (pp. 63-69). IEEE.