Low-VDD Operation of SRAM Synaptic Array for Implementing Ternary Neural Network

Xiaoyu Sun, Rui Liu, Yi Ju Chen, Hsiao Yun Chiu, Wei Hao Chen, Meng Fan Chang, Shimeng Yu

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

For Internet of Things (IoT) edge devices, it is very attractive to have the local sensemaking capability instead of sending all the data back to the cloud for information processing. For image pattern recognition, neuro-inspired machine learning algorithms have demonstrated enormous powerfulness. To effectively implement learning algorithms on-chip for IoT edge devices, on-chip synaptic memory architectures have been proposed to implement the key operations such as weighted-sum or matrix-vector multiplication. In this paper, we proposed a low-power design of static random access memory (SRAM) synaptic array for implementing a low-precision ternary neural network. We experimentally demonstrated that the supply voltage (VDD) of the SRAM array could be aggressively reduced to a level, where the SRAM cell is susceptible to bit failures. The testing results from 65-nm SRAM chips indicate that VDD could be reduced from the nominal 1-0.55 V (or 0.5 V) with a bit error rate ~ 0.23% (or ~ 1.56%), which only introduced ~ 0.08% (or ~ 1.68%) degradation in the classification accuracy. As a result, the power consumption could be reduced by more than 8x (or 10x ).

Original languageEnglish (US)
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOIs
StateAccepted/In press - Jul 28 2017

Fingerprint

Neural networks
Data storage equipment
Learning algorithms
Memory architecture
Bit error rate
Pattern recognition
Learning systems
Electric power utilization
Degradation
Testing
Electric potential
Internet of things

Keywords

  • Arrays
  • Binary synapses
  • classification
  • Image coding
  • low power
  • neural network
  • Neural networks
  • Neurons
  • SRAM cells
  • static random access memory (SRAM).
  • Training

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Low-VDD Operation of SRAM Synaptic Array for Implementing Ternary Neural Network. / Sun, Xiaoyu; Liu, Rui; Chen, Yi Ju; Chiu, Hsiao Yun; Chen, Wei Hao; Chang, Meng Fan; Yu, Shimeng.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 28.07.2017.

Research output: Contribution to journalArticle

Sun, Xiaoyu ; Liu, Rui ; Chen, Yi Ju ; Chiu, Hsiao Yun ; Chen, Wei Hao ; Chang, Meng Fan ; Yu, Shimeng. / Low-VDD Operation of SRAM Synaptic Array for Implementing Ternary Neural Network. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2017.
@article{bf68c536b8634ea3952c7719ff331b53,
title = "Low-VDD Operation of SRAM Synaptic Array for Implementing Ternary Neural Network",
abstract = "For Internet of Things (IoT) edge devices, it is very attractive to have the local sensemaking capability instead of sending all the data back to the cloud for information processing. For image pattern recognition, neuro-inspired machine learning algorithms have demonstrated enormous powerfulness. To effectively implement learning algorithms on-chip for IoT edge devices, on-chip synaptic memory architectures have been proposed to implement the key operations such as weighted-sum or matrix-vector multiplication. In this paper, we proposed a low-power design of static random access memory (SRAM) synaptic array for implementing a low-precision ternary neural network. We experimentally demonstrated that the supply voltage (VDD) of the SRAM array could be aggressively reduced to a level, where the SRAM cell is susceptible to bit failures. The testing results from 65-nm SRAM chips indicate that VDD could be reduced from the nominal 1-0.55 V (or 0.5 V) with a bit error rate ~ 0.23{\%} (or ~ 1.56{\%}), which only introduced ~ 0.08{\%} (or ~ 1.68{\%}) degradation in the classification accuracy. As a result, the power consumption could be reduced by more than 8x (or 10x ).",
keywords = "Arrays, Binary synapses, classification, Image coding, low power, neural network, Neural networks, Neurons, SRAM cells, static random access memory (SRAM)., Training",
author = "Xiaoyu Sun and Rui Liu and Chen, {Yi Ju} and Chiu, {Hsiao Yun} and Chen, {Wei Hao} and Chang, {Meng Fan} and Shimeng Yu",
year = "2017",
month = "7",
day = "28",
doi = "10.1109/TVLSI.2017.2727528",
language = "English (US)",
journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",
issn = "1063-8210",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - Low-VDD Operation of SRAM Synaptic Array for Implementing Ternary Neural Network

AU - Sun, Xiaoyu

AU - Liu, Rui

AU - Chen, Yi Ju

AU - Chiu, Hsiao Yun

AU - Chen, Wei Hao

AU - Chang, Meng Fan

AU - Yu, Shimeng

PY - 2017/7/28

Y1 - 2017/7/28

N2 - For Internet of Things (IoT) edge devices, it is very attractive to have the local sensemaking capability instead of sending all the data back to the cloud for information processing. For image pattern recognition, neuro-inspired machine learning algorithms have demonstrated enormous powerfulness. To effectively implement learning algorithms on-chip for IoT edge devices, on-chip synaptic memory architectures have been proposed to implement the key operations such as weighted-sum or matrix-vector multiplication. In this paper, we proposed a low-power design of static random access memory (SRAM) synaptic array for implementing a low-precision ternary neural network. We experimentally demonstrated that the supply voltage (VDD) of the SRAM array could be aggressively reduced to a level, where the SRAM cell is susceptible to bit failures. The testing results from 65-nm SRAM chips indicate that VDD could be reduced from the nominal 1-0.55 V (or 0.5 V) with a bit error rate ~ 0.23% (or ~ 1.56%), which only introduced ~ 0.08% (or ~ 1.68%) degradation in the classification accuracy. As a result, the power consumption could be reduced by more than 8x (or 10x ).

AB - For Internet of Things (IoT) edge devices, it is very attractive to have the local sensemaking capability instead of sending all the data back to the cloud for information processing. For image pattern recognition, neuro-inspired machine learning algorithms have demonstrated enormous powerfulness. To effectively implement learning algorithms on-chip for IoT edge devices, on-chip synaptic memory architectures have been proposed to implement the key operations such as weighted-sum or matrix-vector multiplication. In this paper, we proposed a low-power design of static random access memory (SRAM) synaptic array for implementing a low-precision ternary neural network. We experimentally demonstrated that the supply voltage (VDD) of the SRAM array could be aggressively reduced to a level, where the SRAM cell is susceptible to bit failures. The testing results from 65-nm SRAM chips indicate that VDD could be reduced from the nominal 1-0.55 V (or 0.5 V) with a bit error rate ~ 0.23% (or ~ 1.56%), which only introduced ~ 0.08% (or ~ 1.68%) degradation in the classification accuracy. As a result, the power consumption could be reduced by more than 8x (or 10x ).

KW - Arrays

KW - Binary synapses

KW - classification

KW - Image coding

KW - low power

KW - neural network

KW - Neural networks

KW - Neurons

KW - SRAM cells

KW - static random access memory (SRAM).

KW - Training

UR - http://www.scopus.com/inward/record.url?scp=85028936782&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85028936782&partnerID=8YFLogxK

U2 - 10.1109/TVLSI.2017.2727528

DO - 10.1109/TVLSI.2017.2727528

M3 - Article

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

SN - 1063-8210

ER -