Abstract
Handheld and other battery-powered ICs require process scaling to increase functional integration and reduce active power consumption. Scaling also increases leakage current components to the point where standby power is frequently a limiting design factor. A scheme combining low-leakage thick-gate shadow latches and high-performance transistors is presented that decouples performance from standby power in sub-130-nm technologies. Circuit design and operation, including pulse-clocked latches, use of dynamic circuits, and inclusion of scan is presented. The approach is validated by experimental results on a 90-nm process.
Original language | English (US) |
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Pages (from-to) | 498-506 |
Number of pages | 9 |
Journal | IEEE Journal of Solid-State Circuits |
Volume | 40 |
Issue number | 2 |
DOIs | |
State | Published - Feb 2005 |
Keywords
- Leakage currents
- Logic circuits
- Low power
- Sequential logic circuits
ASJC Scopus subject areas
- Electrical and Electronic Engineering