Low standby power state storage for sub-130-nm technologies

Lawrence T. Clark, Franco Ricci, Manish Biyani

Research output: Contribution to journalArticle

15 Scopus citations

Abstract

Handheld and other battery-powered ICs require process scaling to increase functional integration and reduce active power consumption. Scaling also increases leakage current components to the point where standby power is frequently a limiting design factor. A scheme combining low-leakage thick-gate shadow latches and high-performance transistors is presented that decouples performance from standby power in sub-130-nm technologies. Circuit design and operation, including pulse-clocked latches, use of dynamic circuits, and inclusion of scan is presented. The approach is validated by experimental results on a 90-nm process.

Original languageEnglish (US)
Pages (from-to)498-506
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Volume40
Issue number2
DOIs
StatePublished - Feb 1 2005

Keywords

  • Leakage currents
  • Logic circuits
  • Low power
  • Sequential logic circuits

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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