TY - GEN

T1 - Low power scheduling scheme with resources operating at multiple voltages

AU - Manzak, Ali

AU - Chakrabarti, Chaitali

PY - 1999/1/1

Y1 - 1999/1/1

N2 - This paper presents a new resource constrained and latency constrained scheduling scheme that minimizes power consumption for the case when the resources operate at multiple voltages. The scheduling scheme is list based. In each control cycle, the ready nodes are assigned depending on the number of available resources and the difference between the actual number of cycles left and an estimate of the number of cycles required to schedule the remaining nodes. The switching activity of the nodes as well as the priority (which is related to the capacitance) of the nodes is taken into account. We assume that the resources can be operated at 5V, 3.3V, 2.4V and 1.5V. Moreover, we assume that the resources (multipliers and adders) have different voltage-delay curves. Experiments with some HLS benchmark examples show that the proposed scheme achieves significant power reduction. For instance, when the latency constraint is 1.5 times the tight latency constraint, the average reduction is 59.1%.

AB - This paper presents a new resource constrained and latency constrained scheduling scheme that minimizes power consumption for the case when the resources operate at multiple voltages. The scheduling scheme is list based. In each control cycle, the ready nodes are assigned depending on the number of available resources and the difference between the actual number of cycles left and an estimate of the number of cycles required to schedule the remaining nodes. The switching activity of the nodes as well as the priority (which is related to the capacitance) of the nodes is taken into account. We assume that the resources can be operated at 5V, 3.3V, 2.4V and 1.5V. Moreover, we assume that the resources (multipliers and adders) have different voltage-delay curves. Experiments with some HLS benchmark examples show that the proposed scheme achieves significant power reduction. For instance, when the latency constraint is 1.5 times the tight latency constraint, the average reduction is 59.1%.

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M3 - Conference contribution

AN - SCOPUS:0032690441

SN - 0780354729

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

SP - I-354 - I-357

BT - Proceedings - IEEE International Symposium on Circuits and Systems

PB - IEEE

T2 - Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99

Y2 - 30 May 1999 through 2 June 1999

ER -