### Abstract

This paper presents a new resource constrained and latency constrained scheduling scheme that minimizes power consumption for the case when the resources operate at multiple voltages. The scheduling scheme is list based. In each control cycle, the ready nodes are assigned depending on the number of available resources and the difference between the actual number of cycles left and an estimate of the number of cycles required to schedule the remaining nodes. The switching activity of the nodes as well as the priority (which is related to the capacitance) of the nodes is taken into account. We assume that the resources can be operated at 5V, 3.3V, 2.4V and 1.5V. Moreover, we assume that the resources (multipliers and adders) have different voltage-delay curves. Experiments with some HLS benchmark examples show that the proposed scheme achieves significant power reduction. For instance, when the latency constraint is 1.5 times the tight latency constraint, the average reduction is 59.1%.

Original language | English (US) |
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Title of host publication | Proceedings - IEEE International Symposium on Circuits and Systems |

Place of Publication | Piscataway, NJ, United States |

Publisher | IEEE |

Volume | 1 |

ISBN (Print) | 0780354729 |

State | Published - 1999 |

Event | Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99 - Orlando, FL, USA Duration: May 30 1999 → Jun 2 1999 |

### Other

Other | Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99 |
---|---|

City | Orlando, FL, USA |

Period | 5/30/99 → 6/2/99 |

### Fingerprint

### ASJC Scopus subject areas

- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials

### Cite this

*Proceedings - IEEE International Symposium on Circuits and Systems*(Vol. 1). Piscataway, NJ, United States: IEEE.

**Low power scheduling scheme with resources operating at multiple voltages.** / Manzak, Ali; Chakrabarti, Chaitali.

Research output: Chapter in Book/Report/Conference proceeding › Chapter

*Proceedings - IEEE International Symposium on Circuits and Systems.*vol. 1, IEEE, Piscataway, NJ, United States, Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99, Orlando, FL, USA, 5/30/99.

}

TY - CHAP

T1 - Low power scheduling scheme with resources operating at multiple voltages

AU - Manzak, Ali

AU - Chakrabarti, Chaitali

PY - 1999

Y1 - 1999

N2 - This paper presents a new resource constrained and latency constrained scheduling scheme that minimizes power consumption for the case when the resources operate at multiple voltages. The scheduling scheme is list based. In each control cycle, the ready nodes are assigned depending on the number of available resources and the difference between the actual number of cycles left and an estimate of the number of cycles required to schedule the remaining nodes. The switching activity of the nodes as well as the priority (which is related to the capacitance) of the nodes is taken into account. We assume that the resources can be operated at 5V, 3.3V, 2.4V and 1.5V. Moreover, we assume that the resources (multipliers and adders) have different voltage-delay curves. Experiments with some HLS benchmark examples show that the proposed scheme achieves significant power reduction. For instance, when the latency constraint is 1.5 times the tight latency constraint, the average reduction is 59.1%.

AB - This paper presents a new resource constrained and latency constrained scheduling scheme that minimizes power consumption for the case when the resources operate at multiple voltages. The scheduling scheme is list based. In each control cycle, the ready nodes are assigned depending on the number of available resources and the difference between the actual number of cycles left and an estimate of the number of cycles required to schedule the remaining nodes. The switching activity of the nodes as well as the priority (which is related to the capacitance) of the nodes is taken into account. We assume that the resources can be operated at 5V, 3.3V, 2.4V and 1.5V. Moreover, we assume that the resources (multipliers and adders) have different voltage-delay curves. Experiments with some HLS benchmark examples show that the proposed scheme achieves significant power reduction. For instance, when the latency constraint is 1.5 times the tight latency constraint, the average reduction is 59.1%.

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UR - http://www.scopus.com/inward/citedby.url?scp=0032690441&partnerID=8YFLogxK

M3 - Chapter

AN - SCOPUS:0032690441

SN - 0780354729

VL - 1

BT - Proceedings - IEEE International Symposium on Circuits and Systems

PB - IEEE

CY - Piscataway, NJ, United States

ER -