Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques

Xiyuan Tang; Jiaxin Liu; Yi Shen; Shaolan Li; Linxiao Shen; Arindam Sanyal; Kareem Ragab; Nan Sun

doi:10.1109/TCSI.2022.3166792

Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques

Xiyuan Tang, Jiaxin Liu, Yi Shen, Shaolan Li, Linxiao Shen, Arindam Sanyal, Kareem Ragab, Nan Sun

Electrical Engineering

Research output: Contribution to journal › Article › peer-review

4 Scopus citations

Abstract

This paper presents an overview for low-power successive approximation register (SAR) analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and practical design issues. Furthermore, this paper provides a comprehensive survey of state-of-the-art low-power design techniques for every circuit block in the SAR ADC, including comparator, capacitive digital-to-analog converter (DAC), and SAR logic. The goal of this paper is to provide a useful overview to SAR ADC designers who want to improve the energy efficiency targeting low-to-medium speed applications.

Original language	English (US)
Pages (from-to)	2249-2262
Number of pages	14
Journal	IEEE Transactions on Circuits and Systems I: Regular Papers
Volume	69
Issue number	6
DOIs	https://doi.org/10.1109/TCSI.2022.3166792
State	Published - Jun 1 2022

Keywords

Analog-to-digital converter (ADC)
energy efficiency
low power
successive approximation register (SAR)

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/TCSI.2022.3166792

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title = "Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques",

abstract = "This paper presents an overview for low-power successive approximation register (SAR) analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and practical design issues. Furthermore, this paper provides a comprehensive survey of state-of-the-art low-power design techniques for every circuit block in the SAR ADC, including comparator, capacitive digital-to-analog converter (DAC), and SAR logic. The goal of this paper is to provide a useful overview to SAR ADC designers who want to improve the energy efficiency targeting low-to-medium speed applications.",

keywords = "Analog-to-digital converter (ADC), energy efficiency, low power, successive approximation register (SAR)",

author = "Xiyuan Tang and Jiaxin Liu and Yi Shen and Shaolan Li and Linxiao Shen and Arindam Sanyal and Kareem Ragab and Nan Sun",

note = "Funding Information: This work was supported in part by the National Key Research and Development Program of China under Grant 2019YFB2205003, in part by the NSFC under Grant 61904094 and Grant 61934009, and in part by the 111 Project under Grant B18001. Publisher Copyright: {\textcopyright} 2004-2012 IEEE.",

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AU - Shen, Yi

AU - Li, Shaolan

AU - Shen, Linxiao

AU - Sanyal, Arindam

AU - Ragab, Kareem

AU - Sun, Nan

N1 - Funding Information: This work was supported in part by the National Key Research and Development Program of China under Grant 2019YFB2205003, in part by the NSFC under Grant 61904094 and Grant 61934009, and in part by the 111 Project under Grant B18001. Publisher Copyright: © 2004-2012 IEEE.

PY - 2022/6/1

Y1 - 2022/6/1

N2 - This paper presents an overview for low-power successive approximation register (SAR) analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and practical design issues. Furthermore, this paper provides a comprehensive survey of state-of-the-art low-power design techniques for every circuit block in the SAR ADC, including comparator, capacitive digital-to-analog converter (DAC), and SAR logic. The goal of this paper is to provide a useful overview to SAR ADC designers who want to improve the energy efficiency targeting low-to-medium speed applications.

AB - This paper presents an overview for low-power successive approximation register (SAR) analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and practical design issues. Furthermore, this paper provides a comprehensive survey of state-of-the-art low-power design techniques for every circuit block in the SAR ADC, including comparator, capacitive digital-to-analog converter (DAC), and SAR logic. The goal of this paper is to provide a useful overview to SAR ADC designers who want to improve the energy efficiency targeting low-to-medium speed applications.

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KW - low power

KW - successive approximation register (SAR)

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Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques

Abstract

Keywords

ASJC Scopus subject areas

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