TY - JOUR
T1 - Low-Power SAR ADC Design
T2 - Overview and Survey of State-of-the-Art Techniques
AU - Tang, Xiyuan
AU - Liu, Jiaxin
AU - Shen, Yi
AU - Li, Shaolan
AU - Shen, Linxiao
AU - Sanyal, Arindam
AU - Ragab, Kareem
AU - Sun, Nan
N1 - Publisher Copyright:
© 2004-2012 IEEE.
PY - 2022/6/1
Y1 - 2022/6/1
N2 - This paper presents an overview for low-power successive approximation register (SAR) analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and practical design issues. Furthermore, this paper provides a comprehensive survey of state-of-the-art low-power design techniques for every circuit block in the SAR ADC, including comparator, capacitive digital-to-analog converter (DAC), and SAR logic. The goal of this paper is to provide a useful overview to SAR ADC designers who want to improve the energy efficiency targeting low-to-medium speed applications.
AB - This paper presents an overview for low-power successive approximation register (SAR) analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and practical design issues. Furthermore, this paper provides a comprehensive survey of state-of-the-art low-power design techniques for every circuit block in the SAR ADC, including comparator, capacitive digital-to-analog converter (DAC), and SAR logic. The goal of this paper is to provide a useful overview to SAR ADC designers who want to improve the energy efficiency targeting low-to-medium speed applications.
KW - Analog-to-digital converter (ADC)
KW - energy efficiency
KW - low power
KW - successive approximation register (SAR)
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U2 - 10.1109/TCSI.2022.3166792
DO - 10.1109/TCSI.2022.3166792
M3 - Article
AN - SCOPUS:85128633432
SN - 1549-8328
VL - 69
SP - 2249
EP - 2262
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 6
ER -