Abstract
In this paper we describe a multi-module, multi-port memory design procedures that satisfies area and/or energy constraints. Our procedure consists of use of ILP models and heuristic-based algorithms to determine (a) the memory configuration with minimum area, given the energy bound, (b) the memory configuration with minimum energy, given the area bound, (c) array allocation such that the energy consumption is minimum for a given memory configuration (number of modules, size and number of ports per module). The results obtained by the heuristics match very well with those obtained by the ILP methods.
| Original language | English (US) |
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| Title of host publication | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation |
| Publisher | IEEE |
| Pages | 529-538 |
| Number of pages | 10 |
| State | Published - 2000 |
| Event | 2000 IEEE Workshop on Signal Processing Systems (SIPS 2000) - Lafayette, LA, USA Duration: Oct 11 2000 → Oct 13 2000 |
Other
| Other | 2000 IEEE Workshop on Signal Processing Systems (SIPS 2000) |
|---|---|
| City | Lafayette, LA, USA |
| Period | 10/11/00 → 10/13/00 |
ASJC Scopus subject areas
- General Engineering