Low power multi-module, multi-port memory design for embedded systems

Wen Tsong Shiue, Shashikiran Tadas, Chaitali Chakrabarti

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Scopus citations

Abstract

In this paper we describe a multi-module, multi-port memory design procedures that satisfies area and/or energy constraints. Our procedure consists of use of ILP models and heuristic-based algorithms to determine (a) the memory configuration with minimum area, given the energy bound, (b) the memory configuration with minimum energy, given the area bound, (c) array allocation such that the energy consumption is minimum for a given memory configuration (number of modules, size and number of ports per module). The results obtained by the heuristics match very well with those obtained by the ILP methods.

Original languageEnglish (US)
Title of host publicationIEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
PublisherIEEE
Pages529-538
Number of pages10
StatePublished - 2000
Event2000 IEEE Workshop on Signal Processing Systems (SIPS 2000) - Lafayette, LA, USA
Duration: Oct 11 2000Oct 13 2000

Other

Other2000 IEEE Workshop on Signal Processing Systems (SIPS 2000)
CityLafayette, LA, USA
Period10/11/0010/13/00

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Shiue, W. T., Tadas, S., & Chakrabarti, C. (2000). Low power multi-module, multi-port memory design for embedded systems. In IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation (pp. 529-538). IEEE.