Low-power high-performance NAND match line content addressable memories

Vikas Chaudhary, Lawrence T. Clark

Research output: Contribution to journalArticle

10 Scopus citations

Abstract

Content addressable memory (CAM) is used in fully associative VLSI lookup circuits for cache memory, translation lookaside buffers (TLBs), and in Internet Protocol (IP) address comparison. In this paper, the use of dynamic NAND match lines is investigated and compared to conventional NOR match lines in cache applications. To achieve high speed, a hierarchical match line is used. The dynamic stack charge-sharing noise immunity, speed, and actual power savings over a conventional NOR match line are investigated using benchmark data. While random patterns are often used when benchmarking CAM match line power, it is shown to be optimistic compared to address trace data, since addresses are highly correlated. It is also shown that proper address input ordering can provide additional power savings. A simple model for the power in dynamic circuit stacks is derived and compared to power simulation data. Additionally, impact on cache tag area and the scaling of the NAND stack to future processes is described.

Original languageEnglish (US)
Article number1664909
Pages (from-to)895-905
Number of pages11
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume14
Issue number8
DOIs
StatePublished - Aug 1 2006

Keywords

  • Cache tag
  • Content addressable memory (CAM)
  • Domino power
  • NAND match line

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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