Low-power dynamic memory word line decoding for static random access memories

Giby Samson, Nagaraj Ananthapadmanabhan, Sayeed A. Badrudduza, Lawrence T. Clark

Research output: Contribution to journalArticle

9 Scopus citations

Abstract

Conventional memory address decoders based on static CMOS gates incur high clock loading and unnecessary power dissipation in unselected banks. This paper presents a dynamic word line decoder which is fast, has reduced active and leakage power dissipation, and also enables faster race-free sense timing. In a multi-bank memory array with sixteen decoders, the energy-delay product of the dynamic decoder is 66 % lower than a low-power static version. The design leverages the predictability of dynamic circuits to provide significant decoder leakage reduction in unselected banks. The dynamic decoder has been fabricated on a 90 nm bulk CMOS process. The measured test chip address to word line delay is 170 ps at 1.5 V and the measured leakage reduction is over 20x at V DD greater than 0.8 V.

Original languageEnglish (US)
Article number4685421
Pages (from-to)2524-2532
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Volume43
Issue number11
DOIs
StatePublished - Nov 1 2008

Keywords

  • Address decoder
  • Dynamic circuits
  • Leakage reduction
  • Power dissipation
  • Static random access memory

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Low-power dynamic memory word line decoding for static random access memories'. Together they form a unique fingerprint.

  • Cite this

    Samson, G., Ananthapadmanabhan, N., Badrudduza, S. A., & Clark, L. T. (2008). Low-power dynamic memory word line decoding for static random access memories. IEEE Journal of Solid-State Circuits, 43(11), 2524-2532. [4685421]. https://doi.org/10.1109/JSSC.2008.2005813