Low power ARM® Cortex™-M0 CPU and SRAM using Deeply Depleted Channel (DDC) transistors with Vdd scaling and body bias

V. Agrawal, N. Kepler, D. Kidd, G. Krishnan, S. Leshner, T. Bakishev, D. Zhao, P. Ranade, R. Roy, M. Wojko, L. Clark, R. Rogenmoser, M. Hori, T. Ema, S. Moriwaki, T. Tsuruta, T. Yamada, J. Mitani, S. Wakayama

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Scopus citations

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Engineering & Materials Science