@inproceedings{8ceb92bebc484757aee7da0e20e7ccd4,
title = "Low power ARM{\textregistered} Cortex{\texttrademark}-M0 CPU and SRAM using Deeply Depleted Channel (DDC) transistors with Vdd scaling and body bias",
abstract = "An SoC with ARM{\textregistered} Cortex{\texttrademark}-M0 CPU cores and SRAMs is implemented in both 65nm baseline and Deeply Depleted Channel{\texttrademark} (DDC) technologies. DDC technology demonstrates more than 50% active and static power reduction for the CPU cores at matched 350 MHz speed via VDD scaling and body biasing. Alternatively DDC technology demonstrates 35% speed increase at matched power. The results hold across process corners and temperature with appropriate body bias selection. DDC technology also increases SRAM static noise margin (SNM) reduces 8Mb VDDmin by 150 mV reduces SRAM active leakage by 50% while maintaining Iread and reduces SRAM retention leakage by 5x.",
author = "V. Agrawal and N. Kepler and D. Kidd and G. Krishnan and S. Leshner and T. Bakishev and D. Zhao and P. Ranade and R. Roy and M. Wojko and L. Clark and R. Rogenmoser and M. Hori and T. Ema and S. Moriwaki and T. Tsuruta and T. Yamada and J. Mitani and S. Wakayama",
year = "2013",
month = nov,
day = "7",
doi = "10.1109/CICC.2013.6658514",
language = "English (US)",
isbn = "9781467361460",
series = "Proceedings of the Custom Integrated Circuits Conference",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013",
note = "35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013 ; Conference date: 22-09-2013 Through 25-09-2013",
}